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TSC21020E-20SBHXXX PDF预览

TSC21020E-20SBHXXX

更新时间: 2024-11-08 15:55:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 外围集成电路
页数 文件大小 规格书
37页 481K
描述
Mixed Signal Processor

TSC21020E-20SBHXXX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.62
位大小:32格式:FLOATING-POINT
JESD-30 代码:S-XQFP-F256JESD-609代码:e0
端子数量:256最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:QFF封装等效代码:QFL256,2.1SQ,20
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not QualifiedRAM(字数):0
子类别:Digital Signal Processors最大压摆率:480 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:FLAT
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIEDuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, MIXED
Base Number Matches:1

TSC21020E-20SBHXXX 数据手册

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TSC21020E  
Radiation Tolerant 32/40–Bit IEEE Floating–Point  
DSP Microprocessor  
Introduction  
TEMIC Semiconductors is manufacturing a radiation The product is pin and code compatible with ADI  
tolerant version of the Analog Devices ADSP–21020 product, making system development straight forward  
32/40–Bit Floating–Point DSP.  
and cost effective, using existing development tools and  
algorithms.  
Features  
D Superscalar IEEE Floating-Point-Processor  
D Off-Chip Harvard Architecture Maximizes Signal Processing  
Performance  
D Two Off-Chip Memory Transfers in Parallel with Instruction  
Fetch and Single-Cycle Multiply & ALU Operations  
D Multiply with Add & Subtract for FFT Butterfly  
Computation  
D 40 ns, 25 MIPS Instruction Rate, Single-Cycle Execution  
D 75 MFLOPS Peak, 50 MFLOPS Sustained Performance  
D 1024-Point Complex FFT Benchmark : 0.78 ms  
D Divide (y/x) : 240 ns  
D Efficient Program Sequencing with Zero-Overhead  
Looping : Single-Cycle Loop Setup  
D Single-Cycle Register File Context Switch  
D 15 (or 25) ns External RAM Access Time for  
Zero-Wait-State, 40 ns Instruction Execution  
D IEEE JTAG Standard 1149.1 Test Access Port and On-Chip  
Emulation Circuitry  
D Inverse Square Root (1/x) : 360 ns  
D 32-Bit Single-Precision and 40-Bit Extended-Precision  
IEEE Floating-Point Data Formats  
D 32-Bit Fixed-Point Formats, Integer and Fractional, with  
80-Bit Accumulators  
D IEEE Exception Handling with Interrupt on Exception  
D Three Independent Computation Units : Multiplier, ALU,  
and Barrel Shifter  
D 223 CPGA package for breadboarding  
D 256 Multi layer quad flat pack, flat leads, for flight models  
D Full compatible with Analog Devices ADSP-21020  
D Latch up better than 55 MeV  
D Dual Data Address Generators with Indirect, Immediate,  
D Total dose better than 50 Krad (Si)  
Modulo, and Bit Reverse Addressing Modes  
D SEU immunity better than 30 MeV/mg/cm2  
– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO  
– Product licensed from Analog Devices Inc.  
MHS  
1
Rev. D (05 Mai 98)  

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