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SGLS194A − SEPTEMBER 2003 − REVISED JULY 2005
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Fully Compliant With Open Host Controller
Interface (HCI) Requirements
D
Cable Power Presence Monitoring
D
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Extended Temperature Performance of
−40°C to 85°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
D
D
Register Bits Give Software Control of
Contender Bit, Power Class Bits, Link
Active Control Bit, and 1394a−2000
Features
Enhanced Product-Change Notification
†
Qualification Pedigree
Data Interface to Link-Layer Controller Pin
Selectable From 1394a−2000 Mode (2/4/8
Parallel Bits at 49.152 MHz) or 1394b Mode
(8 Parallel Bits at 98.304 MHz)
Fully Supports Provisions of IEEE P1394b
Revision 1.33+ at 1-Gigabit Signaling Rates
Fully Supports Provisions of IEEE
1394a−2000 and 1394−1995 Standard for
High Performance Serial Bus
D
D
D
Interface to Link-Layer Controller Supports
Low Cost TI Bus-Holder Isolation
Fully Interoperable With Firewire, i.LINK,
and SB1394, Implementation of IEEE Std
1394
Interoperable With Link-Layer Controllers
Using 3.3-V Supplies
Interoperable With Other 1394 Physical
Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V
Supplies
Provides Three Fully Backward
Compatible, (1394a−2000 Fully Compliant)
Bilingual P1394b Cable Ports at up to
800 Megabits per Second (Mbits/s)
D
Low Jitter, External Crystal Oscillator
Provides Transmit and Receive Data at
100/200/400/800 Mbits/s, and Link-Layer
Controller Clock at 49.152 MHz and
98.304 MHz
D
D
Provides Three 1394a−2000 Fully
Compliant Cable Ports at 100/200/400
Mbits/s
Full 1394a−2000 Support Includes:
− Connection Debounce
− Arbitrated Short Reset
− Multispeed Concatenation
− Arbitration Acceleration
− Fly-By Concatenation
− Port Disable/Suspend/Resume
− Extended Resume Signaling for
Compatibility With Legacy DV Devices
D
D
Separate Bias (TPBIAS) for Each Port
Low Cost, High Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package
D
Software Device Reset (SWR)
D
Fail-Safe Circuitry Senses Sudden Loss of
Power to the Device and Disables the Ports
to Ensure That the TSB81BA3 Does Not
Load the TPBIAS of Any Connected Device
and Blocks any Leakage From the Port
Back to Power Plane
D
D
Power-Down Features to Conserve Energy
in Battery Powered Applications
Low-Power Sleep Mode
D
D
The TSB81BA3 Has a 1394a−2000
Compliant Common-Mode Noise Filter on
the Incoming Bias Detect Circuit to Filter
Out Cross-Talk Noise
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
The TSB81BA3 Is Port Programmable to
Force 1394a Mode to Allow Use of 1394a
Connectors (1394b Signalling Must Not Be
Put Across 1394a Connectors or Cables)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation.
FireWire is a trademark of Apple Computer Incorporated.
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Copyright 2005, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢥꢥ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢧ
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