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TS87C51U2-EJ PDF预览

TS87C51U2-EJ

更新时间： 2024-11-08 20:09:23
品牌 Logo 应用领域
TEMIC 可编程只读存储器微控制器外围集成电路
页数 文件大小 规格书
67页 617K
描述
Microcontroller, 8-Bit, UVPROM, CMOS, CDIP40, WINDOWED, CERAMIC, DIP-40

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中文翻译

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TS87C51U2-EJ 技术参数

生命周期：Transferred包装说明：WINDOWED, CERAMIC, DIP-40
Reach Compliance Code：unknown风险等级：5.71
Is Samacsys：N具有ADC：NO
地址总线宽度：16位大小：8
DAC 通道：NODMA 通道：NO
外部数据总线宽度：8JESD-30 代码：R-GDIP-T40
I/O 线路数量：32端子数量：40
PWM 通道：NO封装主体材料：CERAMIC, GLASS-SEALED
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not QualifiedROM可编程性：UVPROM
表面贴装：NO技术：CMOS
端子形式：THROUGH-HOLE端子位置：DUAL
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

TS87C51U2-EJ 数据手册

 浏览型号TS87C51U2-EJ的Datasheet PDF文件第2页浏览型号TS87C51U2-EJ的Datasheet PDF文件第3页浏览型号TS87C51U2-EJ的Datasheet PDF文件第4页浏览型号TS87C51U2-EJ的Datasheet PDF文件第5页浏览型号TS87C51U2-EJ的Datasheet PDF文件第6页浏览型号TS87C51U2-EJ的Datasheet PDF文件第7页 
TS80C51U2  
TS83C51U2  
TS87C51U2  
Double UART 8-bit CMOS Microcontroller, 0-60 MHz  
1. Description  
TEMIC TS80C51U2 is high performance CMOS ROM, The fully static design of the TS80C51U2 allows to  
OTP and EPROM versions of the 80C51 CMOS single reduce system power consumption by bringing the clock  
chip 8-bit microcontroller.  
frequency down to any value, even DC, without loss of  
data.  
The TS80C51U2 retains all features of the TEMIC  
80C51 with extended ROM/EPROM capacity (16 The TS80C51U2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
Kbytes), 256 bytes of internal RAM, a 7-source , 4-level  
interrupt system, an on-chip oscilator and three timer/  
counters.  
In addition, the TS80C51U2 has a second UART,  
enhanced functions on both UART, enhanced timer 2,  
a hardware watchdog timer, a dual data pointer, a baud  
rate generator and a X2 speed improvement mechanism.  
2. Features  
● 80C52 Compatible  
● Asynchronous port reset  
● Interrupt Structure with  
•
•
•
•
8051 pin and instruction compatible  
Four 8-bit I/O ports  
•
•
7 Interrupt sources  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
● Full duplex Enhanced UARTs  
•
•
Framing error detection  
● High-Speed Architecture  
Automatic address recognition  
•
•
40 MHz @ 5V, 30MHz @ 3V  
● Low EMI (inhibit ALE)  
● Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
•
•
•
Idle mode  
Power-down mode  
Power-off Flag  
● second UART  
● Baud Rate Generator  
● Dual Data Pointer  
● Once mode (On-chip Emulation)  
● Power supply: 4.5-5.5V, 2.7-5.5V  
● On-chip ROM/EPROM (16K-bytes)  
● Temperature ranges: Commercial (0 to 70oC) and  
● Programmable Clock Out and Up/Down Timer/  
Industrial (-40 to 85oC)  
Counter 2  
● Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44  
● Hardware Watchdog Timer (One-time enabled with  
(window), CDIL40 (window)  
Reset-Out)  
3. The second UART  
In this document, UART_0 will make reference to the The second UART (UART_1) can be seen as an alternate  
first UART (present in all TEMIC Semiconductors C51 function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or  
derivatives) and UART_1 will make reference to the P1.7 for TXD1) or can be connected to (pin6 or pin12)  
second UART, only present in the TS80C51U2 part.  
Rev. C - Aug. 24, 1999  
1
1234567...67

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