Datasheet > TPS629203DRLR

TPS629203DRLR

更新时间： 2023-06-19 15:19:53

品牌	Logo	应用领域
德州仪器 - TI		转换器
页数	文件大小	规格书
32页	1608K
描述
采用 SOT-583 封装的 3V 至 17V、0.3A、低 IQ 同步降压转换器 \| DRL \| 8 \| -40 to 150

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TPS629203DRLR 数据手册

TPS629210

www.ti.com

UNIT

SLVSGE0A – AUGUST 2021 – REVISED SEPTEMBER 2021

7.4 Thermal Information

TPS629210

THERMAL METRIC⁽¹⁾

SOT583 8 PIN

JEDEC PCB

TPS6292xxEVM-xxx

R_θJA

R_θJB

Junction-to-ambient thermal resistance

Junction-to-board thermal resistance

131.7

38.5

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

V_I= 3 V to 17 V, T_J= –40°C to + 125°C, Typical values at V_I= 12 V and T_A= 25 °C,unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

Operating quiescent current (Power

Save mode)

I_OUT= 0 mA, T_J= –40°C to 125°C,

device not switching

I_Q

µA

Operating quiescent current (PWM

mode)

V_IN= 12 V, V_OUT= 1.2 V; I_OUT= 0

mA, , device switching

I_Q;PWM

I_SD

V_UVLO

Shutdown current into VIN pin

Undervoltage lockout

EN = 0 V, T_J= –40°C to 85°C

V_INrising

0.3

2.925

2.775

230

6.5

3.0

µA

2.85

2.7

Undervoltage lockout

V_INfalling

2.85

Undervoltage lockout hysteresis

CONTROL AND INTERFACE

I_LKG

EN input leakage current

EN = HIGH, T_J= –40°C to 125°C

100

High-level input voltage at the

MODE/S-CONF pin

V_IH;MODE

1.0

Low-level input voltage at the

MODE/S-CONF pin

V_IL;MODE

0.15

Thermal shutdown threshold

T_Jrising

T_Jfalling

170

T_SD

°C

Thermal shutdown hysteresis

V_IH

V_IL

High-level input voltage at the EN pin

Low-level input voltage at the EN pin

0.97

0.87

94%

89%

1.0

1.03

0.93

98%

96%

0.9

V_FBrising, referenced to V_FBnominal

V_FBfalling, referenced to V_FBnominal

hysteresis

96%

92%

V_PG

Power-good threshold

V_{PG_HYS}

V_PG,OL

I_PG,LKG

t_PG,DLY

Power-good threshold hysteresis

Low-level output voltage at the PG pin I_SINK= 1 mA

0.4

Input leakage current into the PG pin

Power-good delay time

V_PG= 5 V, T_J= –40°C to 125°C

100

µs

POWER SWITCHES

I_LKG;SWLeakage current into the SW pin

EN = 0 V, V_SW= V_OS= 5.5 V, T_J=

–40°C to 125°C

µA

High-side FET on resistance

Low-side FET on resistance

High-side FET current limit

Low-side FET current limit

Low-side FET sink current limit

Minimum on time

300

100

1.8

1.6

0.9

R_DS;ON

mΩ

1.4

1.2

0.7

2.2

2.0

1.2

I_LIM

I_LIM;SINK

T_ON(MIN)

f_SW

Switching frequency

1.0-MHz selection

1.0

100

MHz

I_LKG;VOS

OUTPUT

Leakage current into the VOS pin

800

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