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TPIC1505DW PDF预览

TPIC1505DW

更新时间: 2024-09-15 22:19:19
品牌 Logo 应用领域
德州仪器 - TI 晶体小信号场效应晶体管光电二极管放大器
页数 文件大小 规格书
16页 302K
描述
QUAD AND HEX POWER DMOS ARRAY

TPIC1505DW 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOIC-24针数:24
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.38Is Samacsys:N
配置:COMPLEX最小漏源击穿电压:20 V
最大漏极电流 (Abs) (ID):1.5 A最大漏极电流 (ID):1 A
最大漏源导通电阻:0.48 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:MS-013ADJESD-30 代码:R-PDSO-G24
元件数量:11端子数量:24
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:N-CHANNEL
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:YES端子形式:GULL WING
端子位置:DUAL晶体管应用:AMPLIFIER
晶体管元件材料:SILICONBase Number Matches:1

TPIC1505DW 数据手册

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TPIC1505  
QUAD AND HEX POWER DMOS ARRAY  
SLIS058 – JUNE 1996  
DW PACKAGE  
(TOP VIEW)  
Low r  
:
DS(on)  
0.25 Typ (Full H-Bridge)  
0.35 Typ (Triple Half H-Bridge)  
OUTPUT1  
GATE2C  
GATE1B  
GATE3B  
GND  
GATE3A  
GATE1A  
GATE4A  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
Pulsed Current:  
2
6 A Per Channel (Full H-Bridge)  
4 A Per Channel (Triple Half H-Bridge)  
3
V
4
DD1  
Matched Sense Transistor for Class A-B  
Linear Operation  
V
5
DD3  
OUTPUT3  
SOURCE  
OUTPUT5  
GND  
OUTPUT4  
6
V
7
Fast Commutation Speed  
DD3  
GATE5A  
8
description  
V
9
DD2  
GATE4B  
GATE2B  
GATE2A  
SENSE  
10  
11  
The TPIC1505 is a monolithic power array that  
consists of ten electrically isolated N-channel  
enhancement-mode power DMOS transistors,  
four of which are configured as a full H-bridge and  
six as a triple half H-bridge. The lower stage of the  
full H-bridge features an integrated sense FET to  
allow biasing of the bridge in class A-B operation.  
GATE5B 12  
13 OUTPUT2  
The TPIC1505 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation  
over the case temperature range of 40°C to 125°C.  
schematic  
V
V
V
DD1  
DD2  
DD3  
18, 20  
21  
16  
Q1A  
23  
Q2A  
Q3A  
24  
Q4A  
22  
Q5A  
15  
17  
GATE1A  
GATE2A  
GATE3A  
6
GATE4A  
GATE5A  
1
13  
19  
8
D3  
D1  
D2  
OUTPUT1  
OUTPUT2  
OUTPUT3  
OUTPUT4  
OUTPUT5  
Q1B  
3
Q2B  
11  
Q3B  
4
Q4B  
10  
Q5B  
12  
GATE1B  
GATE2B  
GATE3B  
GATE4B  
GATE5B  
14  
SENSE  
2
7
Q2C  
SOURCE  
GATE2C  
6 V  
5, 9  
GND  
NOTES: A. Pins 5 and 9 must be externally connected.  
B. Pins 18 and 20 must be externally connected.  
C. No output may be taken greater than 0.5 V below GND.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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