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TP11362AV/NOPB PDF预览

TP11362AV/NOPB

更新时间: 2024-11-08 19:55:19
品牌 Logo 应用领域
德州仪器 - TI PC电信电信集成电路
页数 文件大小 规格书
16页 447K
描述
A/MU-LAW, ADPCM CODEC, PQCC28, PLASTIC, LCC-28

TP11362AV/NOPB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.81
压伸定律:A/MU-LAW滤波器:NO
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.43 mm湿度敏感等级:2A
功能数量:1端子数量:28
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:5 V
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Other Telecom ICs最大压摆率:9 mA
标称供电电压:5 V表面贴装:YES
技术:CMOS电信集成电路类型:ADPCM CODEC
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.43 mmBase Number Matches:1

TP11362AV/NOPB 数据手册

 浏览型号TP11362AV/NOPB的Datasheet PDF文件第2页浏览型号TP11362AV/NOPB的Datasheet PDF文件第3页浏览型号TP11362AV/NOPB的Datasheet PDF文件第4页浏览型号TP11362AV/NOPB的Datasheet PDF文件第5页浏览型号TP11362AV/NOPB的Datasheet PDF文件第6页浏览型号TP11362AV/NOPB的Datasheet PDF文件第7页 
March 1997  
TP11362A  
Quad Adaptive Differential PCM Processor  
General Description  
Features  
n CCITT G.726 compatible at 40, 32, 24, 16 kbps  
n ANSI T1.301 compatible at 32 kbps  
n 8-channel half-duplex (encode or decode) or 4-channel  
full-duplex operation in 8 kHz frame  
The TP11362A is a quad (4) channel Adaptive Differential  
Pulse Code Modulation (ADPCM) transcoder, fully compat-  
ible to ITU G.726 recommendation in 40 kbps, 32 kbps,  
24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11362A  
ADPCM processor can operate on up to 8 independent  
channels in an 8 kHz frame. Each channel is individually  
configured, supporting both full and half duplex operation. All  
input/output transfers occur on an interrupt basis using se-  
rial, double buffered data registers. Together with National’s  
TP3054/57 COMBO® or TP3070/71 COMBO II devices, the  
TP11362A forms complete ADPCM channels with Codec/  
filtering.  
n Each channel individually configurable  
n Selectable µ-law or A-law PCM coding  
n Asynchronous 8 MHz master clock operation  
n TTL and CMOS compatible inputs and outputs  
n 28-pin PLCC or 24-pin DIP packages  
n Power consumption of typ. 6 mW at +5V per full-duplex  
channel  
n On-Chip Power-On-Reset  
n −40˚C to +85˚C operating temperature range  
n Single 5V supply  
Block Diagram  
DS012877-1  
FIGURE 1. Block Diagram  
TRI-STATE® and COMBO® are registered trademarks of National Semiconductor Corporation.  
© 1997 National Semiconductor Corporation  
DS012877  
www.national.com  

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