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TN2540N3-GP014 PDF预览

TN2540N3-GP014

更新时间： 2024-11-09 02:57:59
品牌 Logo 应用领域
超科 - SUPERTEX 开关晶体管
页数 文件大小 规格书
6页 741K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

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中文翻译

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TN2540N3-GP014 技术参数

生命周期：Transferred包装说明：CYLINDRICAL, O-PBCY-T3
Reach Compliance Code：unknown风险等级：5.82
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：400 V
最大漏极电流 (ID)：0.175 A最大漏源导通电阻：12 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：25 pF
JEDEC-95代码：TO-92JESD-30 代码：O-PBCY-T3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
极性/信道类型：N-CHANNEL表面贴装：NO
端子形式：THROUGH-HOLE端子位置：BOTTOM
晶体管应用：SWITCHING晶体管元件材料：SILICON

TN2540N3-GP014 数据手册

 浏览型号TN2540N3-GP014的Datasheet PDF文件第2页浏览型号TN2540N3-GP014的Datasheet PDF文件第3页浏览型号TN2540N3-GP014的Datasheet PDF文件第4页浏览型号TN2540N3-GP014的Datasheet PDF文件第5页浏览型号TN2540N3-GP014的Datasheet PDF文件第6页 
Supertex inc.  
TN2540  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
► Low threshold (2.0V max.)  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
► High input impedance  
► Low input capacitance (125pF max.)  
► Fast switching speeds  
► Low on-resistance  
► Free from secondary breakdown  
► Low input and output leakage  
Applications  
► Logic level interfaces - ideal for TTL and CMOS  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
► Solid state relays  
► Battery operated systems  
► Photo voltaic drives  
► Analog and Telecom switches  
► General purpose line drivers  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
VGS(th)  
Part Number  
Package Options  
Packing  
BVDSS/BVDGS  
(max)  
(min)  
(max)  
TN2540N3-G  
TO-92  
1000/Bag  
2000/Reel  
2000/Reel  
2000/Reel  
2000/Reel  
2000/Reel  
400V  
12Ω  
1.0A  
2.0V  
TN2540N3-G P002 TO-92  
TN2540N3-G P003 TO-92  
TN2540N3-G P005 TO-92  
TN2540N3-G P013 TO-92  
TN2540N3-G P014 TO-92  
Pin Configuration  
DRAIN  
TN2540N8-G  
TO-243AA (SOT-89) 2000/Reel  
DRAIN  
-G denotes a lead (Pb)-free / RoHS compliant package  
Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014 TO-92  
Taping Specifications and Winding Styles  
SOURCE  
SOURCE  
DRAIN  
GATE  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
GATE  
Absolute Maximum Ratings  
TO-92  
TO-243AA (SOT-89)  
Parameter  
Value  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
Gate-to-source voltage  
Operating and storage temperature  
BVDSS  
BVDGS  
SiTN  
2 5 4 0  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
±20V  
-55OC to +150OC  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
Package may or may not include the following marks: Si or  
TO-92  
W = Code for week sealed  
TN5DW  
Typical Thermal Resistance  
= “Green” Packaging  
Package may or may not include the following marks: Si or  
TO-243AA (SOT-89)  
Package  
θja  
TO-92  
132OC/W  
133OC/W*  
TO-243AA (SOT-89)  
* Mounted on FR5 Board, 25mm x 25mm x 1.57mm  
Doc.# DSFP-TN2540  
A062113  
Supertex inc.  
www.supertex.com  
123456

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