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TMXF281553BAL-3C-DB PDF预览

TMXF281553BAL-3C-DB

更新时间: 2024-10-27 23:36:35
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其他 - ETC 电信数据通信
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描述
Telecomm/Datacomm

TMXF281553BAL-3C-DB 数据手册

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Data Sheet  
June 2002  
TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
1.2 STS/STM Pointer Interpreter  
1 Features  
Interprets STS/AU/TU-3 pointers.  
Versatile IC supports 155/51 Mbits/s SONET/SDH  
interface solutions for T3, DS2, T1/E1/J1, and DS0/  
E0/J0 applications.  
Synchronizes 8 kHz frame and 2 kHz superframe to  
system/shelf timing reference by setting the transmit  
STS-3/STM-1 pointers to a fixed value of 522.  
Implementation supports both linear (1 + 1, unpro-  
tected) and ring (UPSR) network topologies.  
Monitors/terminates SPE path overhead.  
Provides full termination of up to 21 E1, 28 T1, or  
28 J1.  
1.3 Telecom Bus Interface  
Low-power 3.3 V supply.  
Telecom bus interface to mate devices including  
clock, data[8], parity, SPE-, J0-, J1-, and V1 timing  
indicator.  
–40 °C to +85 °C industrial temperature range.  
456-pin ball grid array (PBGA) package, 35 mm2 with  
a 1.27 mm ball pitch.  
Line and path RDI and REI signals passed to mate  
devices.  
Complies with Telcordia ™, ITU, ANSI ®, ETSI, and  
Japanese TTC standards: GR-253-CORE, GR-499,  
(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,  
G.962, G.964, G.965, Q.542, T1.105, JT-G704,  
JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,  
ETS 300 011, T1.107, T1.404.  
Three Supermapper devices, two configured as mate  
devices, provide full termination of an  
STS-3/STM-1. A three-chip solution to terminate  
84 DS1s/J1s or 63 E1s.  
1.1 SONET/SDH Interface  
1.4 VT Termination/Generation (x28/x21)  
Termination of a single 155 Mbits/s STS-3/STM-1 or  
single 51 Mbits/s STS-1/STM-0.  
Monitors/terminates VT path overhead for  
28 VT1.5/TU-11 or 21 VT2/TU-12.  
Built-in clock and data recovery circuit at  
155 Mbits/s STS-3/STM-1 interface (can be dese-  
lected if external clock recovery is provided).  
Synchronizes VT/TU SPE to system/shelf timing ref-  
erence by setting the transmit VT/TU pointers to  
fixed values for asynchronous mapping or by dynam-  
ically changing the transmit VT/TU pointers for byte  
synchronous mapping.  
Supports overhead processing for all transport and  
path overhead bytes.  
Fixed pointer generation in transmit side for asyn-  
chronous mapping.  
Optional insertion and extraction of overhead bytes  
via a serial transport overhead access channel. Con-  
figurable as dedicated DCC channels.  
Dynamic pointer generation in transmit side for byte-  
synchronous mapping.  
Software-controlled linear 1 + 1 protection via dedi-  
cated interface to protection card.  
Full path termination and SPE extraction/insertion.  
1.5 Mapping/Multiplexing Modes (x28/x21)  
SONET/SDH compliant condition and alarm report-  
ing.  
Maps DS3 clear channel or framed signal into STS-1  
or TUG-3.  
Built-in diagnostic loopback modes.  
8 kHz line frame sync output.  
Maps T1/E1/J1 into VT/TU (including DS1 into  
TU-12).  
Supports asynchronous, byte-synchronous, and bit-  
synchronous mapping.  

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