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TMX5703137APGEQQ1

更新时间： 2024-10-27 20:04:43
品牌 Logo 应用领域
德州仪器 - TI 时钟微控制器外围集成电路
页数 文件大小 规格书
168页 3305K
描述
32-BIT, FLASH, 160MHz, RISC MICROCONTROLLER, PQFP144, GREEN, PLASTIC, LQFP-144

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TMX5703137APGEQQ1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP, QFP144,.87SQ,20针数：144
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.81
具有ADC：YES其他特性：ALSO OPERATES AT 3.3 V NOMINAL I/O SUPPLY
地址总线宽度：16位大小：32
CPU系列：CORTEX-R4F最大时钟频率：80 MHz
DAC 通道：NODMA 通道：YES
外部数据总线宽度：16JESD-30 代码：S-PQFP-G144
JESD-609代码：e4长度：20 mm
湿度敏感等级：3I/O 线路数量：44
端子数量：144最高工作温度：105 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：1.2,3.3,3.3/5 V认证状态：Not Qualified
RAM（字节）：262144ROM（单词）：3145728
ROM可编程性：FLASH筛选级别：AEC-Q100
座面最大高度：1.6 mm速度：160 MHz
子类别：Microcontrollers最大压摆率：400 mA
最大供电电压：1.32 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLER, RISCBase Number Matches：1

TMX5703137APGEQQ1 数据手册

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Sample &  
Buy  
Support &  
Community  
Product  
Folder  
Tools &  
Software  
Technical  
Documents  
TMS570LS3137  
www.ti.com  
SPNS162B –APRIL 2012–REVISED JULY 2013  
TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller  
1 TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller  
1.1 Features  
12  
– RAM Trace Port (RTP)  
• High-Performance Automotive-Grade  
Microcontroller for Safety-Critical Applications  
– Parameter Overlay Module (POM)  
• Multiple Communication Interfaces  
– 10/100 Mbps Ethernet MAC (EMAC)  
– Dual CPUs Running in Lockstep  
– ECC on Flash and RAM interfaces  
– Built-In Self-Test for CPU and On-chip RAMs  
– Error Signaling Module with Error Pin  
– Voltage and Clock Monitoring  
•
•
IEEE 802.3 Compliant (3.3-V I/O only)  
Supports MII, RMII and MDIO  
– FlexRay Controller with Two Channels  
• ARM® Cortex™ – R4F 32-Bit RISC CPU  
•
•
8 KB message RAM with Parity Protection  
Dedicated Transfer Unit (FTU)  
– Efficient 1.66 DMIPS/MHz with 8-Stage  
Pipeline  
– Three CAN Controllers (DCANs)  
– FPU with Single- and Double-Precision  
– 12-Region Memory Protection Unit  
– Open Architecture with Third-Party Support  
• Operating Conditions  
•
•
64 Mailboxes, Each with Parity Protection  
Compliant to CAN Protocol Version 2.0B  
– Local Interconnect Network (LIN) Interface  
Controller  
– Up to 180-MHz System Clock  
•
•
Compliant to LIN Protocol Version 2.1  
Can be Configured as a Second SCI  
– Core Supply Voltage (VCC): 1.2 V Nominal  
– I/O Supply Voltage (VCCIO): 3.3 V Nominal  
– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V  
• Integrated Memory  
– Standard Serial Communication Interface  
(SCI)  
– Inter-Integrated Circuit (I2C)  
– Three Multibuffered Serial Peripheral  
Interfaces (MibSPIs)  
– 3MB of Program Flash with ECC  
– 256KB of RAM with ECC  
– 64KB of Flash with ECC for Emulated  
EEPROM  
•
128 Words with Parity Protection Each  
– Two Standard Serial Peripheral Interfaces  
(SPIs)  
• Two High-End Timer Modules (N2HETs)  
– N2HET1: 32 Programmable Channels  
– N2HET2: 18 Programmable Channels  
• 16-Bit External Memory Interface  
• Common Platform Architecture  
– Consistent Memory Map Across Family  
– Real-Time Interrupt Timer (RTI) OS Timer  
– 96-Channel Vectored Interrupt Module (VIM)  
– 2-Channel Cyclic Redundancy Checker  
(CRC)  
– 160-Word Instruction RAM with Parity  
Protection Each  
– Each N2HET Includes Hardware Angle  
Generator  
– Dedicated Transfer Unit with MPU for Each  
N2HET (HTU)  
• Direct Memory Access (DMA) Controller  
– 16 Channels and 32 Control Packets  
– Parity Protection for Control Packet RAM  
– DMA Accesses Protected by Dedicated MPU  
• Frequency-Modulated Phase-Locked-Loop  
(FMPLL) with Built-In Slip Detector  
• Separate Nonmodulating PLL for FlexRay™  
• IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight™ Components  
• JTAG Security Module  
• Trace and Calibration Capabilities  
– Embedded Trace Macrocell (ETM-R4)  
• Two 10- or 12-bit Multibuffered ADC Modules  
– ADC1: 24 Channels  
– ADC2: 16 Channels Shared with ADC1  
– 64 Result Buffers with Parity Protection Each  
• Sixteen General-Purpose Input/Output Pins  
(GPIO) Capable of Generating Interrupts  
• Packages  
– 144-Pin Quad Flatpack (PGE) [Green]  
– 337-Ball Grid Array (ZWT) [Green]  
– Data Modification Module (DMM)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2012–2013, Texas Instruments Incorporated  
 
 
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