Datasheet > TMS32C6711DZDPA167

TMS32C6711DZDPA167

更新时间： 2024-10-28 11:08:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
129页	1914K
描述
C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA \| ZDP \| 272 \| -40 to 105

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TMS32C6711DZDPA167 数据手册

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TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

Excellent-Price/Performance Floating-Point

Digital Signal Processors (DSPs):

TMS320C67x (C6711, C6711B, C6711C,

and C6711D)

− Eight 32-Bit Instructions/Cycle

− 100-,150-,167-,200-,250-MHz Clock Rates

− 10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle

Time

32-Bit External Memory Interface (EMIF)

− Glueless Interface to Asynchronous

Memories: SRAM and EPROM

− Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

− 256M-Byte Total Addressable External

Memory Space

16-Bit Host-Port Interface (HPI)

− 600, 900, 1000, 1200, 1500 MFLOPS

Two Multichannel Buffered Serial Ports

(McBSPs)

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− ST-Bus-Switching Compatible

− Up to 256 Channels Each

− AC97-Compatible

− Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

Advanced Very Long Instruction Word

(VLIW) C67x DSP Core

− Eight Highly Independent Functional

Units:

− Four ALUs (Floating- and Fixed-Point)

− Two ALUs (Fixed-Point)

− Two Multipliers (Floating- and

Fixed-Point)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

Two 32-Bit General-Purpose Timers

Flexible Phase-Locked-Loop (PLL) Clock

Generator [C6711/11B]

Flexible Software Configurable PLL-Based

Clock Generator Module [C6711C/11D]

Instruction Set Features

− Hardware Support for IEEE

Single-Precision and Double-Precision

Instructions

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation

− Bit-Field Extract, Set, Clear

− Bit-Counting

− Normalization

A Dedicated General-Purpose Input/Output

(GPIO) Module With 5 Pins [C6711C/11D]

†

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

256-Pin Ball Grid Array (BGA) Package

(GFN Suffix) [C6711/C6711B Only]

272-Pin Ball Grid Array (BGA) Package

(GDP Suffix) [C6711C/C6711D Only]

L1/L2 Memory Architecture

− 32K-Bit (4K-Byte) L1P Program Cache

(Direct Mapped)

− 32K-Bit (4K-Byte) L1D Data Cache

(2-Way Set-Associative)

− 512K-Bit (64K-Byte) L2 Unified Mapped

RAM/Cache

CMOS Technology

− 0.13-µm/6-Level Copper Metal Process

(C6711C/C6711D)

− 0.18-µm/5-Level Copper Metal Process

(C6711/11B)

3.3-V I/O, 1.4-V Internal (C6711D−250)

3.3-V I/O, 1.20-V Internal (C6711C/C6711D)^‡

3.3-V I/O, 1.8-V Internal (C6711B/C6711−100)

3.3-V I/O, 1.9-V Internal (C6711-150)

(Flexible Data/Program Allocation)

Device Configuration

− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

− Endianness: Little Endian, Big Endian

Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320C67x and C67x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

†

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

These values are compatible with existing 1.26V designs.

This document contains information on products in more than one phase

of development. The status of each device is indicated on the page(s)

specifying its electrical characteristics.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...129

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TMS32C6711DZDPA167 替代型号

型号	品牌	替代类型	描述	数据表
TMS32C6711DGDPA167	TI	完全替代	FLOATING-POINT DIGITAL SIGNAL PROCESSORS
TMS32C6711CGDPA167	TI	功能相似	FLOATING-POINT DIGITAL SIGNAL PROCESSORS

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