TMS320VC5421
DIGITAL SIGNAL PROCESSOR
SPRS098 – DECEMBER 1999
D
D
200-MIPS Dual-Core DSP Consisting of Two D Conditional Store Instructions
Independent Subsystems
D
D
D
Output Control of CLKOUT
Output Control of TOUT
Each Core Has an Advanced Multibus
Architecture With Three Separate 16-Bit
Data Memory Buses and One Program Bus
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions
D
D
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel-Shifter and Two
40-Bit Accumulators Per Core
D
Dual 1.8-V (Core) and 3.3-V (I/O) Power
Supplies for Low-Power, Fast Operations
D
D
10-ns Single-Cycle Fixed-Point Instruction
Each Core Has a 17-Bit × 17-Bit Parallel
Multiplier Coupled to a 40-Bit Adder for
Non-Pipelined Single-Cycle Multiply/
Accumulate (MAC) Operations
Interprocessor Communication via Two
Internal 8-Element FIFOs
D
Twelve Channels of Direct Memory Access
(DMA) for Data Transfers With No CPU
Loading (Six Channels Per Subsystem With
External Access)
D
D
D
Each Core Has a Compare, Select, and
Store Unit (CSSU) for the Add/Compare
Selection of the Viterbi Operator
D
Six Multichannel Buffered Serial Ports
(McBSPs) With 128-Channel Selection
Capability (3 McBSPs per Subsystem)
Each Core Has an Exponent Encoder to
Compute an Exponent Value of a 40-Bit
Accumulator Value in a Single Cycle
D
D
16-Bit Host-Port Interface (HPI) Multiplexed
With External Memory Interface Pins
Each Core Has Two Address Generators
With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic Units
(ARAUs)
Software-Programmable Phase-Locked
Loop (APLL) Provides Several Clocking
Options (Requires External TTL Oscillator)
D
D
D
16-Bit Data Bus With Data Bus Holder
Feature
D
D
Includes JTAG Functionality for In-Circuit
Emulation
512K-Word × 16-Bit Extended Program
Address Space
On-Chip Scan-Based Emulation Logic,
{
IEEE Standard 1149-1 (JTAG) Boundary-
Total of 256K-Word × 16-Bit Dual- and
Single-Access On-Chip RAM (128K-Word x
16-Bit Shared Memory)
Scan Logic
D
D
D
Two Software-Programmable Timers
(One Per Subsystem)
D
D
Single-Instruction Repeat and
Block-Repeat Operations
Software-Programmable Wait-State
Generator (14 Wait States Maximum)
Instructions With 32-Bit-Long Word
Operands
Provided in 144-pin MicroStartBall Grid
Array (GGU Suffix) and 144-pin Thin Quad
Flatpack (TQFP) (PGE Suffix) Packages
D
D
D
Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
Arithmetic Instructions With Parallel Store
and Parallel Load
description
The TMS320VC5421 fixed-point digital signal processor (DSP) is a dual-core solution running at 200-MIPS
performance. The ’5421 consists of two DSP subsystems capable of core-to-core communications and a
128K-word zero-wait-state on-chip program memory shared by the two DSP subsystems. Each subsystem
consists of one ’54x DSP core, 32K-word program/data DARAM, 32K-word data SARAM, 2K-word ROM, three
multichannel serial interfaces, xDMA logic, one timer, one APLL, and other miscellaneous circuitry.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar is a trademark of Texas Instruments Incorporated.
†
IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture.
Copyright 1999, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
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