TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TMS320F2837xS Microcontrollers
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Four Serial Communications Interfaces (SCI/
UART) (pin-bootable)
1 Features
•
TMS320C28x 32-bit CPU
– 200 MHz
– IEEE 754 single-precision Floating-Point Unit
(FPU)
– Two I2C interfaces (pin-bootable)
Analog subsystem
•
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
Programmable Control Law Accelerator (CLA)
– 200 MHz
– IEEE 754 single-precision floating-point
instructions
– Executes code independently of main CPU
On-chip memory
– 512KB (256KW) or 1MB (512KW) of flash
(ECC-protected)
– Up to four Analog-to-Digital Converters (ADCs)
•
16-bit mode
•
•
– 1.1 MSPS each (up to 4.4-MSPS system
throughput)
– Differential inputs
– Up to 12 external channels
12-bit mode
•
– 3.5 MSPS each (up to 14-MSPS system
throughput)
– Single-ended inputs
– 132KB (66KW) or 164KB (82KW) of RAM
(ECC-protected or parity-protected)
– Dual-zone security supporting third-party
development
– Unique identification number
Clock and system control
– Up to 24 external channels
Single Sample-and-Hold (S/H) on each ADC
Hardware-integrated post-processing of
ADC conversions
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare,
with interrupt capability
•
•
•
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator
– Windowed watchdog timer module
– Missing clock detection circuitry
1.2-V core, 3.3-V I/O design
System peripherals
– Two External Memory Interfaces (EMIFs) with
ASRAM and SDRAM support
– Trigger-to-sample delay capture
– Eight windowed comparators with 12-bit Digital-
to-Analog Converter (DAC) references
– Three 12-bit buffered DAC outputs
Enhanced control peripherals
– 24 PWM channels with enhanced features
– 16 High-Resolution Pulse Width Modulator
(HRPWM) channels
•
•
•
– 6-channel Direct Memory Access (DMA)
controller
– Up to 169 individually programmable,
multiplexed General-Purpose Input/Output
(GPIO) pins with input filtering
– Expanded Peripheral Interrupt controller (ePIE)
– Multiple Low-Power Mode (LPM) support with
external wakeup
Communications peripherals
– USB 2.0 (MAC + PHY)
– Support for 12-pin 3.3 V-compatible Universal
Parallel Port (uPP) interface
– Two Controller Area Network (CAN) modules
(pin-bootable)
•
High resolution on both A and B channels of
8 PWM modules
Dead-band support (on both standard and
high resolution)
•
– Six Enhanced Capture (eCAP) modules
– Three Enhanced Quadrature Encoder Pulse
(eQEP) modules
– Eight Sigma-Delta Filter Module (SDFM) input
channels, 2 parallel filters per channel
•
•
•
Standard SDFM data filtering
Comparator filter for fast action for out of
range
– Three high-speed (up to 50-MHz) SPI ports
(pin-bootable)
•
•
Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
Functional Safety-Compliant
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
Copyright © 2021 Texas Instruments Incorporated
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