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TMS320C6743DPTP2 PDF预览

TMS320C6743DPTP2

更新时间： 2024-12-02 11:07:11
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153页 1286K
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低功耗 C674x 浮点 DSP- 375MHz | PTP | 176 | 0 to 90

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TMS320C6743DPTP2 数据手册

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TMS320C6743  
www.ti.com  
SPRS565B–APRIL 2009–REVISED JUNE 2011  
TMS320C6743 Fixed/Floating-Point Digital Signal Processor  
Check for Samples: TMS320C6743  
1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor  
1.1 Features  
12  
Cycle  
• Highlights  
– Two Multiply Functional Units  
– Up to 375-MHz FIxed/Floating-Point VLIW  
DSP Core  
•
•
Mixed-Precision IEEE Floating Point  
Multiply Supported up to:  
– Enhanced Direct-Memory-Access Controller  
(EDMA3)  
– Two External Memory Interfaces  
– Two Configurable 16550 type UART Modules  
– One Serial Peripheral Interface (SPI)  
– Multimedia Card (MMC)/Secure Digital (SD)  
– Two Master/Slave Inter-Integrated Circuit  
Modules (I2C)  
– RMII Ethernet Media Access COntroller  
–
–
–
–
2 SP x SP -> SP Per Clock  
2 SP x SP -> DP Every Two Clocks  
2 SP x DP -> DP Every Three Clocks  
2 DP x DP -> DP Every Four Clocks  
Fixed Point Multiply Supports Two 32 x  
32-Bit Multiplies, Four 16 x 16-Bit  
Multiplies, or Eight 8 x 8-Bit Multiplies per  
Clock Cycle, and Complex Multiples  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
(EMAC)  
– Three Event Capture (eCAP) Modules  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
– Two Quadrature Encoding (eQEP) Modules  
– Two Multi-Channel Audio Serial Ports  
(McASP)  
– Exceptions Support for Error Detection and  
– Programmable Real-Time Unit Subsystem  
Program Redirection  
(PRUSS)  
• C674x Instruction Set Features  
– Two 64-bit Timers (each configurable as  
32-bit)  
• Applications  
– Superset of the C67x+™ and C64x+™ ISAs  
– 3000/2250 C674x MIPS/MFLOPS  
– Industrial Control  
– Networking  
– Byte-Addressable (8-/16-/32-/64-Bit Data)  
– 8-Bit Overflow Protection  
– High-Speed Encoding  
– Professional Audio™  
• Software Support  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– Compact 16-Bit Instructions  
– TI DSP/BIOS™  
– Chip Support Library and DSP Library  
• TMS320C674x Floating Point VLIW DSP Core  
• C674x Two Level Cache Memory Architecture  
– 32K-Byte L1P Program RAM/Cache  
– 32K-Byte L1D Data RAM/Cache  
– Load-Store Architecture With Non-Aligned  
– 128K-Byte L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
Support  
– 64 General-Purpose Registers (32 Bit)  
– Six ALU (32-/40-Bit) Functional Units  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
•
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
Supports up to Four SP Additions Per  
Clock, Four DP Additions Every 2 Clocks  
Supports up to Two Floating Point (SP or  
DP) Reciprocal Approximation (RCPxP)  
and Square-Root Reciprocal  
– 2 Transfer Controllers  
– 32 Independent DMA Channels  
– 8 Quick DMA Channels  
– Programmable Transfer Burst Size  
• 3.3V LVCMOS IOs  
•
•
• Two External Memory Interfaces:  
– EMIFA  
•
NOR (8-Bit-Wide Data)  
Approximation (RSQRxP) Operations Per  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2011, Texas Instruments Incorporated  
 
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 		16-BIT, 50MHz, OTHER DSP, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256
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 		16-BIT, 50MHz, OTHER DSP, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256
TMS320C6745 TI

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 		Floating-point Digital Signal Processor
TMS320C6745_13 TI

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