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TMS320C6416TBCLZA7 PDF预览

TMS320C6416TBCLZA7

更新时间: 2024-10-28 12:02:19
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
146页 1984K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6416TBCLZA7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:CSP
包装说明:HFBGA, BGA532,26X26,32针数:532
Reach Compliance Code:compliantECCN代码:3A991.A.2
HTS代码:8542.31.00.01Factory Lead Time:6 weeks
风险等级:1.57地址总线宽度:20
桶式移位器:NO位大小:32
边界扫描:YES最大时钟频率:75 MHz
外部数据总线宽度:64格式:FIXED POINT
集成缓存:YES内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B532JESD-609代码:e1
长度:23 mm低功率模式:YES
湿度敏感等级:4DMA 通道数量:64
外部中断装置数量:4端子数量:532
计时器数量:3片上程序ROM宽度:8
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HFBGA
封装等效代码:BGA532,26X26,32封装形状:SQUARE
封装形式:GRID ARRAY, HEAT SINK/SLUG, FINE PITCH峰值回流温度(摄氏度):260
电源:1.2,3.3 V认证状态:Not Qualified
RAM(字数):4096ROM可编程性:FLASH
座面最大高度:3.25 mm子类别:Digital Signal Processors
最大供电电压:1.24 V最小供电电压:1.16 V
标称供电电压:1.2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:23 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6416TBCLZA7 数据手册

 浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第2页浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第3页浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第4页浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第5页浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第6页浏览型号TMS320C6416TBCLZA7的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢀꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢀ  
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢀ ꢐꢍ ꢕꢍ ꢀꢖꢗ ꢂꢍ ꢕ ꢔꢖꢗ ꢒꢘ ꢓ ꢆꢏ ꢂ ꢂꢓ ꢘ ꢂ  
SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009  
Highest-Performance Fixed-Point DSPs  
− 1.67-/1.39-/1.17-/1-ns Instruction Cycle  
− 600-/720-/850-MHz, 1-GHz Clock Rate  
− Eight 32-Bit Instructions/Cycle  
− Twenty-Eight Operations/Cycle  
− 4800, 5760, 6800, 8000 MIPS  
− Fully Software-Compatible With C62x  
− C6414/15/16 Devices Pin-Compatible  
− Extended Temperature Devices Available  
Two External Memory Interfaces (EMIFs)  
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)  
− Glueless Interface to Asynchronous  
Memories (SRAM and EPROM) and  
Synchronous Memories (SDRAM,  
SBSRAM, ZBT SRAM, and FIFO)  
− 1280M-Byte Total Addressable External  
Memory Space  
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
VelociTI.2Extensions to VelociTI  
Advanced Very-Long-Instruction-Word  
(VLIW) TMS320C64xDSP Core  
− Eight Highly Independent Functional  
Units With VelociTI.2Extensions:  
− Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad  
8-Bit Arithmetic per Clock Cycle  
− Two Multipliers Support  
Host-Port Interface (HPI)  
− User-Configurable Bus Width (32-/16-Bit)  
32-Bit/33-MHz, 3.3-V PCI Master/Slave  
Interface Conforms to PCI Specification 2.2  
[C6415T/C6416T]  
− Three PCI Bus Address Registers:  
Prefetchable Memory  
Non-Prefetchable Memory I/O  
− Four-Wire Serial EEPROM Interface  
− PCI Interrupt Request Under DSP  
Program Control  
Four 16 x 16-Bit Multiplies  
(32-Bit Results) per Clock Cycle or  
Eight 8 x 8-Bit Multiplies  
(16-Bit Results) per Clock Cycle  
− Non-Aligned Load-Store Architecture  
− 64 32-Bit General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
− DSP Interrupt Via PCI I/O Cycle  
Three Multichannel Buffered Serial Ports  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− Up to 256 Channels Each  
Instruction Set Features  
− Byte-Addressable (8-/16-/32-/64-Bit Data)  
− 8-Bit Overflow Protection  
− Bit-Field Extract, Set, Clear  
− Normalization, Saturation, Bit-Counting  
− VelociTI.2Increased Orthogonality  
VCP [C6416T Only]  
− Supports Over 833 7.95-Kbps AMR  
− Programmable Code Parameters  
− ST-Bus-Switching-, AC97-Compatible  
− Serial Peripheral Interface (SPI)  
Compatible (Motorola)  
Three 32-Bit General-Purpose Timers  
UTOPIA [C6415T/C6416T]  
− UTOPIA Level 2 Slave ATM Controller  
− 8-Bit Transmit and Receive Operations  
up to 50 MHz per Direction  
− User-Defined Cell Format up to 64 Bytes  
TCP [C6416T Only]  
Sixteen General-Purpose I/O (GPIO) Pins  
Flexible PLL Clock Generator  
− Supports up to 10 2-Mbps or  
60 384-Kbps 3GPP (6 Iterations)  
− Programmable Turbo Code and  
Decoding Parameters  
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
L1/L2 Memory Architecture  
− 128K-Bit (16K-Byte) L1P Program Cache  
(Direct Mapped)  
− 128K-Bit (16K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
− 8M-Bit (1024K-Byte) L2 Unified Mapped  
RAM/Cache (Flexible Allocation)  
532-Pin Ball Grid Array (BGA) Package  
(GLZ/ZLZ/CLZ Suffixes), 0.8-mm Ball Pitch  
0.09-µm/7-Level Cu Metal Process (CMOS)  
3.3-V I/Os, 1.1-V Internal (600 MHz)  
3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1  
GHz)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
ꢀꢥ  
Copyright 2009, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

TMS320C6416TBCLZA7 替代型号

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