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TMS320C31-50 PDF预览

TMS320C31-50

更新时间: 2024-11-12 23:36:27
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其他 - ETC 数字信号处理器
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48页 635K
描述
Digital Signal Processor

TMS320C31-50 数据手册

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TMS320C31, TMS320LC31  
DIGITAL SIGNAL PROCESSORS  
SPRS035B – MARCH 1996 – REVISED JANUARY 1999  
High-Performance Floating-Point Digital  
Signal Processor (DSP):  
On-Chip Memory-Mapped Peripherals:  
– One Serial Port  
– TMS320C31-80 (5 V)  
– Two 32-Bit Timers  
25-ns Instruction Cycle Time  
440 MOPS, 80 MFLOPS, 40 MIPS  
– TMS320C31-60 (5 V)  
– One-Channel Direct Memory Access  
(DMA) Coprocessor for Concurrent I/O  
and CPU Operation  
33-ns Instruction Cycle Time  
330 MOPS, 60 MFLOPS, 30 MIPS  
– TMS320C31-50 (5 V)  
40-ns Instruction Cycle Time  
275 MOPS, 50 MFLOPS, 25 MIPS  
– TMS320C31-40 (5 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
– TMS320LC31-40 (3.3 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
– TMS320LC31-33 (3.3 V)  
Fabricated Using 0.6 µm Enhanced  
Performance Implanted CMOS (EPIC )  
Technology by Texas Instruments (TI )  
132-Pin Plastic Quad Flat Package  
(PQ Suffix)  
Eight Extended-Precision Registers  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
Two Low-Power Modes  
Two- and Three-Operand Instructions  
60-ns Instruction Cycle Time  
183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS  
Parallel Arithmetic/Logic Unit (ALU) and  
Multiplier Execution in a Single Cycle  
32-Bit High-Performance CPU  
Block-Repeat Capability  
16-/32-Bit Integer and 32-/40-Bit  
Floating-Point Operations  
Zero-Overhead Loops With Single-Cycle  
Branches  
32-Bit Instruction Word, 24-Bit Addresses  
Conditional Calls and Returns  
Two 1K × 32-Bit Single-Cycle Dual-Access  
On-Chip RAM Blocks  
Interlocked Instructions for  
Multiprocessing Support  
Boot-Program Loader  
Bus-Control Registers Configure  
Strobe-Control Wait-State Generation  
description  
The TMS320C31 and TMS320LC31 DSPs are 32-bit, floating-point processors manufactured in 0.6 µm  
triple-level-metal CMOS technology. The TMS320C31 and TMS320LC31 are part of the TMS320C3x  
generation of DSPs from Texas Instruments.  
The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and  
flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C3x  
optimizes speed by implementing functions in hardware that other processors implement through software or  
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.  
The TMS320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single  
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,  
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.  
High performance and ease of use are results of these features.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and TI are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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