TMPM4K Group(2)
Datasheet
CMOS Digital Integrated Circuit Silicon Monolithic
TMPM4K Group(2)
General Description
LQFP144 20x20mm, 0.5mm pitch
LQFP100 14x14mm, 0.5mm pitch
LQFP80
LQFP80
LQFP64
LQFP64
14x14mm, 0.65mm pitch
12x12mm, 0.5mm pitch
12x12mm, 0.65mm pitch
10x10mm, 0.5mm pitch
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Arm® Cortex®-M4 processor with FPU
Operation frequency: 1 to 160 MHz, Operation voltage: 2.7 to 5.5 V
LQFP128 14x20mm, 0.5mm pitch
QFP100 14x20mm, 0.65mm pitch
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Code flash: 128 to 512 KB, Data flash: 32KB
Package: 64-pin to 144-pin. 8 types of packages are available.
Hardware IPs such as A-VE+, 12-bit ADC, and A-PMD are provided for implementation of vector control and PFC control
Applications
Motors, major appliances using motors, and industrial equipment.
Features
● Arm Cortex-M4 processor with FPU
‒ Operation frequency: 1 to 160 MHz
‒ Memory Protection Unit (MPU)
● DMA controller (DMAC): 1 unit
‒ DMA requests: 30 to 32 factors, internal/external triggers
● CRC Calculation Circuit (CRC): CRC32, CRC16
● Low-power consumption mode
● Asynchronous Serial Interface (UART): 3 to 4 channels
‒ 5Mbps(Max), FIFO(Transmitter 8-stage, Receive 8-stage)
● Serial Peripheral Interface (TSPI): 2 channels
‒ Operation voltage: 2.7 to 5.5 V
‒ Low-power consumption operation: IDLE, STOP1
● Operation temperature: -40 to +105°C
● Internal memory
‒ SIO/SPI mode, 10Mbps(MAX), FIFO(Transmitter: 16bitx8,
Receive: 16bitx8)
● I2C Interface (I2C): 2 channels, Multi Master
● CAN controller (CAN): 0 to 1 channel
‒ Code flash: 128 to 512 KB, rewritable up to 10,000 times
‒ Data flash: 32KB rewritable up to 100,000 times
‒ Data flash is rewritable in parallel with instruction execution
‒ RAM: 24KB, with parity
‒ Version2.0B Active, 32 mailbox, MAX 1Mbps
● 12-bit Analog to Digital Converter (ADC): 14 to 32 inputs in 3 units
‒ Conversion time: 1.0 µs at ADCLK=160MHz
‒ Self-diagnosis support function
● Clock
‒ External high speed oscillator: 6 to 12 MHz(Ceramic, Crystal)
‒ External high speed clock input: 6 to 10 MHz
● Operational Amplifier (OPAMP): 3 channels
‒ Gain selectable
‒ Internal high speed oscillator (IHOSC1): 10 MHz, user
trimming function
● Advanced programmable motor control circuit (A-PMD): 3
channels
‒ PLL: 160 MHz output(System clock)
‒ 3-phase complementary PWM output, Synchronized with ADC
‒ PFC control: support 3-phase interleaved PFC
● Oscillation frequency detection (OFD): Abnormal system clock
detection
● Voltage Detection (LVD): 8 level, Generate interrupts and reset
‒ Emergency stop function by external inputs (EMG pin, OVV pin)
● Advanced vector engine plus (A-VE+): 1 channel
‒ Vector control coprocessor cooperates with ADC/A-PMD
‒ 1-shunt current detection area can be enlarged
outputs
● Interruption
‒ External: 15 to 22 factors, with DNF
‒ Internal: 95 to 105factors
‒ Dead time compensation control, non-interference control
● I/O ports: 51 to 131 (Input:2, Output:1)
‒ 5V-tolerant, open-drain, pull-up/-down
● On-chip debug (JTAG/SW), NBDIF(RAM monitor)
● Trigger Selector (TRGSEL)
● Advanced Encoder input circuit (32-bit) (A-ENC32): 1 to 3
channels
‒ Encoder/sensor (3 types)/Timer /Phase counter mode
‒ Expand Trigger request for DMAC, Timer, others
Start of commercial production
2019-05
© 2018-2021
Toshiba Electronic Devices & Storage Corporation
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2021-10-15
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