Datasheet > TMPM4NRFDFG

TMPM4NRFDFG

更新时间： 2024-11-19 14:57:35

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
153页	2590K
描述

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中文翻译

获取价格

数据手册

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TMPM4NRFDFG 数据手册

TXZ+ Family

TMPM4N Group (1)

Datasheet

CMOS Digital Integrated Circuit Silicon Monolithic

LQFP176(20x20mm, 0.4mm pitch)

LQFP144(20x20mm, 0.5mm pitch)

TXZ+ Family

LQFP100(14x14mm, 0.5mm pitch)

TMPM4N Group (1)

VFBGA177(13x13mm, 0.8mm pitch)

VFBGA145(12x12mm, 0.8mm pitch)

General Description

●

Arm ^®Cortex^®-M4 ( with FPU)

Operating frequency: 1 to 200 MHz, Operating voltage: 2.7 to 3.6 V

Code Flash: 512 KB to 2048 KB. Data Flash: 32KB

Built-in High speed 12-bit AD converter and plenty of timers/serial channels

Built-in CAN controller, Universal Serial Bus, Ethernet MAC

Applications

TXZ+ family TMPM4N Group (1) integrates widely used for the equipment in which high speed data procedure is required, such as

OA/digital products, industrial equipment, and others.

Features

● Arm Cortex-M4 ( with FPU)

● Voltage Detection (LVD): 7 levels. selection between interrupts

and reset outputs

Operating frequency: 1 to 200 MHz

Memory Protection Unit (MPU)

● Interrupt

External factor: 9 to 16

● Supply voltage and power consumption

(External pins: 14 to 28 pins, with DNF).

Internal: 117 to 157 factors

Operating voltage: 2.7 to 3.6 V

Low-power consumption operation: IDLE, STOP1, and STOP2

● I/O ports: 86 to 146 (Input: 4, Output: 1)

● Operating temperature:

- 40 to +85°C@operating frequency 1 to 200 MHz

● Internal memory

Enable to select Pull-up/Pull-down resistor, Open-drain

5V tolerant, 3V tolerant

● On-chip debug (JTAG/SW) and NBDIF (RAM monitor)

Code Flash: 512 KB to 2048 KB, rewritable up to 100,000 times

Data Flash: 32 KB, rewritable up to 100,000 times

● Trigger Selector (TRGSEL)

Expand trigger requests for DMA Controller, Timer counter, and

others.

Data Flash is rewritable during instruction execution

RAM: 192 KB to 256 KB and Backup RAM: 2 KB (all products)

● DMA Controller: 3 Units

● Clock

MDMAC: 1 Unit, DMA requests: 30 to 32 factors, internal/external

triggers

External high speed oscillator: 8 MHz to 20 MHz (Ceramic and

Crystal)

HDMAC: 2 Units, DMA requests: 13 to 15 factors,

internal/external triggers

External high speed clock input: 8 to 24 MHz

Internal high speed oscillator1 (IHOSC1):10MHz, user trimming

function

● External bus interface (EBIF)

Expandable to 64MB (Program/data)

Internal high speed oscillator2 (IHOSC2):10MHz

PLL: 200 MHz output

External data bus (separate bug/multiplexed bun): 8/16 bit width

Chip select controller: 4 channels

External low speed oscillator: 32.768 kHz

● Oscillation Frequency Detector (OFD): Abnormal system clock

detection

Start of commercial production

2021-10

2023-10-31

Rev.1.4

1 / 153

Toshiba Electronic Devices & Storage Corporation

12 3 4 5 6 7...153

中文翻译

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