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TMC2249AG1C1 PDF预览

TMC2249AG1C1

更新时间： 2024-11-17 22:32:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
18页 140K
描述
Digital Mixer 12 x 12 Bit, 60 MHz

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中文翻译

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TMC2249AG1C1 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：PGA包装说明：PGA, PGA120,13X13
针数：120Reach Compliance Code：unknown
ECCN代码：3A991.A.2HTS代码：8542.39.00.01
风险等级：5.64边界扫描：NO
最大时钟频率：40 MHz外部数据总线宽度：12
JESD-30 代码：S-CPGA-P120JESD-609代码：e0
长度：34.16 mm低功率模式：NO
端子数量：120最高工作温度：70 °C
最低工作温度：输出数据总线宽度：16
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装等效代码：PGA120,13X13封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：5.46 mm子类别：DSP Peripherals
最大压摆率：105 mA最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：34.16 mmuPs/uCs/外围集成电路类型：DSP PERIPHERAL, MIXER
Base Number Matches：1

TMC2249AG1C1 数据手册

 浏览型号TMC2249AG1C1的Datasheet PDF文件第2页浏览型号TMC2249AG1C1的Datasheet PDF文件第3页浏览型号TMC2249AG1C1的Datasheet PDF文件第4页浏览型号TMC2249AG1C1的Datasheet PDF文件第5页浏览型号TMC2249AG1C1的Datasheet PDF文件第6页浏览型号TMC2249AG1C1的Datasheet PDF文件第7页 
www.fairchildsemi.com  
TMC2 2 4 9 A  
Dig it a l Mix e r  
1 2 x 1 2 Bit , 6 0 MHz  
Features  
Applications  
• 60 MHz input and computation rate  
• Two 12-bit multipliers  
• Video switching  
• Image mixing  
• Separate data and coefficient inputs  
• Independent, user-selectable pipeline delays of 1 to 16  
clocks on all input ports  
• Digital signal modulation  
• Complex frequency synthesis  
• Digital filtering  
• Separate 16-bit input port allows cascading or addition of  
a constant  
• Complex arithmetic functions  
• User-selectable rounded output  
• Internal 1/2 LSB rounding of products  
• Fully registered, pipelined architecture  
• Available in 120-Pin CPGA, PPGA, MPGA or MQFP  
Description  
The TMC2249A is a high-speed digital arithmetic circuit  
consisting of two 12-bit multipliers, an adder and a cascade-  
able accumulator. All four multiplier inputs are simulta-  
neously accessible to the user, and each includes a user-  
programmable pipeline delay of up to 16 clocks in length.  
The 24-bit adder/subtractor is followed by an accumulator  
and 16-bit input port which allows the user to cascade multi-  
ple TMC2249As. A new 16-bit accumulated output is avail-  
able every clock, up to the maximum rate of 60 MHz. All  
inputs and outputs are registered except the three-state out-  
put enable, and all are TTL compatible.  
The TMC2249A utilizes a pipelined, bus-oriented structure  
offering significant flexibility. Input register clock enables  
and programmable input data pipeline delays on each port  
offer an adaptable input structure for high-speed digital  
systems. Following the multipliers, the user may perform  
addition or subtraction of either product, arithmetic rounding  
to 16 bits, and accumulation and summation of products with a  
cascading input. The output port allows access to all 24 bits of  
the internal accumulator by switching between overlapping  
least and most-significant 16-bit words, and a three-state out-  
put enable simplifies connection to an external system bus.  
The TMC2249A has numerous applications in digital pro-  
cessing algorithms, from executing simple image mixing and  
switching, to performing complex arithmetic functions and  
complex waveform synthesis. FIR filters, digital quadrature  
mixers and modulators, and vector arithmetic functions may  
also be implemented with this device.  
Logic Symbol  
CLK  
TMC2249A  
Digital Mixer  
NEG1  
NEG2  
SWAP  
A
Delay  
1-16  
11-0  
ADEL  
Fabricated in a submicron CMOS process, the TMC2249A  
operates at guaranteed clock rates of up to 60 MHz over the  
full temperature and supply voltage ranges. It is pin- and  
function-compatible with Fairchild’s TMC2249, while pro-  
viding higher speed operation and lower power dissipation. It  
is available in a 120 pin Ceramic Pin Grid Array (CPGA),  
120 pin Plastic Pin Grid Array (PPGA), 120 lead MQFP to  
PPGA package (MPGA), and a 120 lead Metric Quad Flat-  
Pack (MQFP).  
3-0  
OE  
ENA  
ACC  
Delay  
1-16  
B
11-0  
BDEL  
3-0  
S
ENB  
15-0  
Delay  
1-16  
C
11-0  
CDEL  
3-0  
ENC  
Delay  
1-16  
D
11-0  
RND  
FT  
DDEL  
3-0  
END  
CASEN  
CAB  
15-0  
REV. 1.0.2 7/6/00  
1234567...18

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