Datasheet > TMC2250AH5C3

TMC2250AH5C3

更新时间： 2024-02-07 19:34:11

品牌	Logo	应用领域
CADEKA		/
页数	文件大小	规格书
23页	293K
描述
Matrix Multiplier 12 x 10 bit, 50 MHz

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TMC2250AH5C3 技术参数

生命周期：	Contact Manufacturer	包装说明：	PGA,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.59	边界扫描：	NO
最大时钟频率：	50 MHz	外部数据总线宽度：	12
JESD-30 代码：	S-PPGA-P120	长度：	34.16 mm
低功率模式：	NO	端子数量：	120
最高工作温度：	70 °C	最低工作温度：
输出数据总线宽度：	12	封装主体材料：	PLASTIC/EPOXY
封装代码：	PGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	座面最大高度：	5.46 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	PIN/PEG	端子节距：	2.54 mm
端子位置：	PERPENDICULAR	宽度：	34.16 mm
uPs/uCs/外围集成电路类型：	DSP PERIPHERAL, MULTIPLIER	Base Number Matches：	1

TMC2250AH5C3 数据手册

www.cadeka.com

TMC2250A

Matrix Multiplier

12 x 10 bit, 50 MHz

Features

Applications

• Four user-selectable ﬁltering and transformation

functions:

• Image ﬁltering and manipulation

• Video effects generation

– Triple dot product (3 x 3) matrix multiply

– Cascadeable 9-tap systolic FIR ﬁlter

– Cascadeable 3 x 3-pixel image convolver

– Cascadeable 4 x 2-pixel image convolver

• 50 MHz (20ns) pipelined throughput

• 12-bit input and output data, 10-bit coefﬁcients

• 6-bit cascade input and output ports in all ﬁlter modes

• Onboard coefﬁcient storage, with three-cycle updating of

all nine coefﬁcients

• Video standards conversion and encoding/decoding

• Three-dimensional image manipulation

• Medical image processing

• Edge detection for object recognition

• FIR ﬁltering for communications systems

Description

The TMC2250A is a ﬂexible high-performance nine-multiplier

array VLSI circuit which can execute a cascadeable 9-tap

FIR ﬁlter, a cascadeable 4 x 2 or 3 x 3-pixel image convolu-

tion, or a 3 x 3 color space conversion. All conﬁgurations

offer throughput at up to the maximum guaranteed 50 MHz

clock rate with 12-bit data and 10-bit coefﬁcients. All inputs

and outputs are registered on the rising edges of the clock.

The cascadeable 3 x 3 and 4 x 2-pixel image convolver func-

tions allow the user to perform numerous image processing

functions, including static ﬁlters and edge detectors. The 16-bit

cascade input port facilitates two-chip 50 MHz cubic convo-

lution (4 x 4-pixel kernel).

The TMC2250A is fabricated in a sub-micron CMOS process

and operates at clock speeds of up to 50 MHz over the full

commercial (0°C to 70°C) temperature and supply voltage

ranges. It is available in 120-pin Plastic Pin Grid Array

(PPGA) packages, 120-lead Ceramic Pin Grid Array pack-

age (CPGA), 120-lead PQFP to PPGA package (MPGA) and

120-lead Plastic Quad FlatPack (PQFP). All input and output

signals are TTL compatible.

The 3 x 3 matrix multiply or color conversion conﬁguration

can perform video standard conversion (YIQ or YUV to

RGB, etc.) or three-dimensional perspective translation at

real-time video rates.

The 9-tap FIR ﬁlter conﬁguration, useful in Video, Telecom-

munications, and Signal Processing, features a 16-bit cascade

input to allow construction of longer ﬁlters.

REV. 1.0.2 10/25/00

12 3 4 5 6 7...23

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与TMC2250AH5C3相关器件

型号	品牌	获取价格	描述	数据表
TMC2250AH6C	FAIRCHILD	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C	CADEKA	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C	ROCHESTER	获取价格	Multiplier, 12-Bit, CMOS, CPGA120, PGA-120
TMC2250AH6C2	CADEKA	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C2	FAIRCHILD	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C2	ROCHESTER	获取价格	Multiplier, 12-Bit, CMOS, CPGA120, PGA-120
TMC2250AH6C3	FAIRCHILD	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C3	CADEKA	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz
TMC2250AH6C3	ROCHESTER	获取价格	Multiplier, 12-Bit, CMOS, CPGA120, PGA-120
TMC2250AKEC	CADEKA	获取价格	Matrix Multiplier 12 x 10 bit, 50 MHz

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