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TMC2246AKEC2 PDF预览

TMC2246AKEC2

更新时间: 2024-01-07 09:54:29
品牌 Logo 应用领域
CADEKA 过滤器
页数 文件大小 规格书
18页 371K
描述
Image Filter 11 x 10 bit, 60 MHz

TMC2246AKEC2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:METRIC, QFP-120针数:120
Reach Compliance Code:unknown风险等级:5.91
其他特性:11 BIT COEFFICIENT INPUT BUS边界扫描:NO
最大时钟频率:60 MHz外部数据总线宽度:10
JESD-30 代码:S-PQFP-G120长度:28 mm
低功率模式:NO湿度敏感等级:NOT SPECIFIED
端子数量:120最高工作温度:70 °C
最低工作温度:输出数据总线宽度:16
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:COMMERCIAL
座面最大高度:3.92 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:NOT SPECIFIED
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTER

TMC2246AKEC2 数据手册

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www.cadeka.com  
TMC2246A  
Image Filter  
11 x 10 bit, 60 MHz  
Features  
Applications  
• 60 MHz computation rate  
• 60 MHz data and coefficient input  
• Four 11 x 10-bit multipliers  
• Individual data and coefficient inputs  
• 25-Bit accumulator  
• Fast pixel interpolation  
• Fast image manipulation  
• Image mixing and keying  
• High-performance FIR filters  
• Adaptive digital filters  
• Fractional and integer two’s complement data formats  
• Input and output data latches with user-configurable  
enables  
• One- and two-dimensional image processing  
• Selectable 16-bit rounded output  
• Internal 1/2 LSB rounding  
• Available in 120-pin CPGA, PPGA, MPGA, or MQFP  
Description  
The TMC2246A is a video-speed convolutional array com-  
posed of four 11 x 10 bit registered multipliers followed by a  
summer and an accumulator. All eight multiplier inputs are  
accessible to the user and may be updated every clock cycle  
with integer or fractional two’s complement data. A pipe-  
lined architecture, fully registered input and output ports,  
and asynchronous three-state output enable control simplify  
the design of complex systems.  
The data or coefficient inputs to the multipliers may be held  
over multiple clock cycles, providing storage for mixing and  
filtering coefficients. The 25-bit internal accumulator path  
allows two bits of cumulative word growth and may be inter-  
nally rounded to 16 bits. Output data are updated every clock  
cycle, or may be held under user control. All data inputs, out-  
puts, and controls are TTL compatible and (except for the  
three-state output enable) are registered on the rising edge of  
CLK.  
The TMC2246A is uniquely suited to performing pixel inter-  
polation in image manipulation and filtering applications. As  
a companion to the Fairchild Semiconductor TMC2301 and  
TMC2302 Image Manipulation Sequencers, the TMC2246A  
can execute a bilinear interpolation of an image (4-pixel ker-  
nels) at real-time video rates. Larger kernels or other, more  
complex, functions can be realized with no loss in performance  
by utilizing multiple devices.  
Logic Symbol  
TMC2246A  
Image Filter  
D1  
9-0  
ENB1-4  
ENSEL  
ACC  
C1  
C2  
C3  
C4  
10-0  
D2  
9-0  
FSEL  
With unrestricted access to all data and coefficient input  
ports, the TMC2246A offers considerable flexibility in appli-  
cations performing digital filtering, adaptive FIR filters, mix-  
ers, and other similar systems requiring high-speed  
processing.  
10-0  
S
15-0  
D3  
9-0  
OCEN  
OEN  
CLK  
10-0  
D4  
9-0  
Fabricated in a submicron CMOS process, the TMC2246A  
operates at a guaranteed clock rate of 60 MHz over the full  
temperature and supply voltage ranges. It is pin- and func-  
tion-compatible with CADEKA’s TMC2246, while providing  
higher speed operation and lower power dissipation. It is  
available in a 120 pin Plastic Pin Grid Array (PPGA), 120  
pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to  
PPGA (MPGA), and a 120 lead Metric Quad FlatPack  
(MQFP).  
10-0  
REV. 1.0.3 9/11/00  

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