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SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003
D
D
Maximum Throughput 200-KSPS
D
D
D
D
D
Single Wide Range Supply 2.7 Vdc to
5.5 Vdc
Built-In Reference, Conversion Clock and
8× FIFO
Differential/Integral Nonlinearity Error:
1 LSB
Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
D
D
D
D
Hardware Controlled and Programmable
Sampling Period
Signal-to-Noise and Distortion Ratio:
70 dB, f = 12-kHz
Low Operating Current (1.0-mA at 3.3-V,
1.1-mA at 5.5-V With External Ref
i
Spurious Free Dynamic Range: 75 dB,
f = 12- kHz
Power Down: Software/Hardware
Power-Down Mode (1 µA Max, Ext Ref),
Autopower-Down Mode (1 µA, Ext Ref)
i
SPI (CPOL = 0, CPHA = 0)/DSP-Compatible
Serial Interfaces With SCLK up to 20-MHz
D
Programmable Auto-Channel Sweep
TLV2548
DW OR PW PACKAGE
(TOP VIEW)
TLV2544
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20 CS
SDO
CS
SDO
SDI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
19
18
17
16
15
14
13
12
11
SDI
REFP
REFM
FS
REFP
REFM
FS
SCLK
SCLK
EOC/(INT)
EOC/(INT)
V
PWDN
GND
V
PWDN
GND
CC
CC
A0
A1
A2
A0
A1
A2
A3
A4
10 CSTART
A3
CSTART
A7
9
A6
A5
description
The TLV2548 and TLV2544 are a family of high performance, 12-bit low power, 3.86 µs, CMOS analog-to-digital
converters (ADC) which operate from a single 2.7-V to 5.5-V power supply. These devices have three digital
inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial
data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors
(SPI interface). When interfaced with a TI DSP, a frame sync (FS) signal is used to indicate the start of a serial
data frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog
multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special
pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be
programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular
among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low
power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down
modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The
converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when
a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional
external reference can also be used to achieve maximum flexibility.
The TLV2544C and the TLV2548C are characterized for operation from 0°C to 70°C. The TLV2544I and the
TLV2548I are characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1999 − 2003, Texas Instruments Incorporated
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