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TLV2548MFK PDF预览

TLV2548MFK

更新时间： 2024-11-26 04:28:07
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
41页 864K
描述
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

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TLV2548MFK 数据手册

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TLV2544Q, TLV2548Q, TLV2548M  
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN  
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002  
Maximum Throughput 200-KSPS  
Hardware Controlled and Programmable  
Sampling Period  
Built-In Reference, Conversion Clock and  
8× FIFO  
Low Operating Current (1-mA at 3.3-V,  
2-mA at 5.5-V With External Ref, 1.7-mA at  
3.3-V, 2.4-mA at 5.5-V With Internal Ref)  
Differential/Integral Nonlinearity Error:  
±1.2 LSB at –55°C to 125°C  
Power Down: Software/Hardware  
Power-Down Mode (1 µA Typ, Ext Ref),  
Autopower-Down Mode (1 µA Typ, Ext Ref)  
Signal-to-Noise and Distortion Ratio:  
65 dB, f = 12-kHz at –55°C to 125°C  
i
Spurious Free Dynamic Range: 75 dB,  
Programmable Auto-Channel Sweep  
f = 12- kHz  
i
Available in Q-Temp Automotive  
SPI/DSP-Compatible Serial Interfaces With  
SCLK up to 20-MHz  
High Reliability Automotive Applications  
Configuration Control/Print Support  
Qualification to Automotive Standards  
Single Wide Range Supply 3 Vdc to  
5.5 Vdc  
Analog Input Range 0-V to Supply Voltage  
With 500 kHz BW  
TLV2544Q . . . D PACKAGE  
(TOP VIEW)  
TLV2548M . . . FK PACKAGE  
(TOP VIEW)  
TLV2548Q . . . DW PACKAGE  
(TOP VIEW)  
SDO  
SDI  
CS  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
SDO  
SDI  
CS  
REFP  
REFM  
FS  
REFP  
REFM  
FS  
SCLK  
SCLK  
3
2
1
20 19  
EOC/(INT)  
EOC/(INT)  
EOC/(INT)  
REFM  
FS  
4
5
6
7
8
18  
17  
16  
15  
14  
V
PWDN  
V
PWDN  
GND  
CSTART  
A7  
CC  
CC  
V
CC  
A0  
A1  
A2  
11 GND  
A0  
A1  
A2  
A3  
A4  
A0  
A1  
A2  
PWDN  
GND  
10 CSTART  
9
A3  
A6  
CSTART  
A5  
9
10 11 12 13  
description  
The TLV2544Q, TLV2548Q, and TLV2548M are a family of high performance, 12-bit low power, 3.5 µs, CMOS  
analog-to-digital converters (ADC) which operate from a single 3-V to 5.5-V power supply. These devices have  
three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input  
(SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host  
microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the  
start of a serial data frame.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...41

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