ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢇ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢇ ꢀ ꢁꢂ ꢉ ꢄ ꢅꢆ ꢇ ꢀꢁ ꢂꢉ ꢄꢅ ꢈ
ꢄ ꢊꢋ ꢌꢍ ꢌꢁ ꢎ ꢏꢇ ꢃ ꢊꢐꢄ ꢊꢋ ꢑꢒ ꢏꢒ ꢀꢌꢁ ꢇ ꢓ ꢆ ꢊꢐꢓ ꢉ ꢊꢔꢒ ꢀꢇ ꢉ ꢕ ꢕ ꢊꢖꢗꢘ ꢗꢇ ꢆ ꢊꢐꢈ ꢊ ꢂꢙ ꢌꢍ ꢍ ꢚꢁ
ꢗ ꢚꢛ ꢒ ꢌꢁ ꢌꢍꢌ ꢁꢎ ꢏ ꢊꢀꢎ ꢊꢑꢒꢏ ꢒ ꢀꢌꢁ ꢂꢎ ꢍꢋꢚ ꢛꢀ ꢚꢛꢗ ꢜ ꢒꢀ ꢙ ꢓ ꢕ ꢊꢋ ꢒ ꢍꢘ ꢝ ꢀꢗ
SLAS262C − OCTOBER 2000 − REVISED MAY 2003
TLC3578, TLC2578
DW OR PW PACKAGE
(TOP VIEW)
D
14-Bit Resolution for TLC3574/78, 12-Bit for
TLC2574/2578
D
Maximum Throughput 200-KSPS
1
24
23
22
21
20
19
18
17
16
15
14
13
SCLK
FS
SDI
CSTART
D
Multiple Analog Inputs:
− 8 Single-Ended Channels for
TLC3578/2578
− 4 Single-Ended Channels for
TLC3574/2574
2
AV
DD
3
AGND
COMP
REFM
REFP
AGND
4
EOC/INT
SDO
DGND
5
6
D
D
D
Analog Input Range: 10 V
7
DV
DD
Pseudodifferential Analog Inputs
8
CS
A0
A1
A2
A3
AV
A7
A6
A5
A4
DD
9
SPI/DSP-Compatible Serial Interfaces With
SCLK up to 25-MHz
10
11
12
D
Built-In Conversion Clock and 8x FIFO
D
Single 5-V Analog Supply; 3-/5-V Digital
Supply
TLC3574, TLC2574
DW, N, OR PW PACKAGE
(TOP VIEW)
D
Low-Power
− 5.8 mA in Normal Operation
− 20 µA in Power Down
D
D
Programmable Autochannel Sweep and
Repeat
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SCLK
FS
SDI
CSTART
AV
DD
AGND
COMP
REFM
REFP
AGND
Hardware-Controlled, Programmable
Sampling Period
EOC/INT
SDO
DGND
D
Hardware Default Configuration
D
INL: TLC3574/78: 1 LSB;
TLC2574/78: 0.5 LSB
DV
DD
CS
A0
A1
AV
A3
A2
DD
D
D
D
DNL: TLC3574/78: 0.5 LSB;
TLC2574/78: 0.5 LSB
SINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
THD: TLC3574/78: −82 dB;
TLC2574/78: −82 dB
description
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS
analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate
from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital
input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state
serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI,
SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being
transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow
the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must
be tied to DV
if it is not used (such as in an SPI interface). When SDI is tied to DV , the device is set in
DD
DD
hardware default mode after power on and no software configuration is required. In the simplest case, only three
wires (SDO, SCLK, and CS or FS) are needed to interface with the host.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢘ
ꢘ
ꢛ
ꢎ
ꢭ
ꢑ
ꢨ
ꢝ
ꢂ
ꢦ
ꢀ
ꢧ
ꢒ
ꢡ
ꢎ
ꢟ
ꢍ
ꢠ
ꢑ
ꢌ
ꢀ
ꢌ
ꢞ
ꢟ
ꢩ
ꢠ
ꢡ
ꢧ
ꢢ
ꢣ
ꢤ
ꢤ
ꢥ
ꢥ
ꢞ
ꢞ
ꢡ
ꢡ
ꢟ
ꢟ
ꢞ
ꢦ
ꢦ
ꢪ
ꢧ
ꢨ
ꢢ
ꢢ
ꢩ
ꢩ
ꢟ
ꢥ
ꢤ
ꢣ
ꢦ
ꢦ
ꢡ
ꢠ
ꢪ
ꢀꢩ
ꢨ
ꢫ
ꢦ
ꢬ
ꢞ
ꢧ
ꢤ
ꢦ
ꢥ
ꢞ
ꢥ
ꢡ
ꢢ
ꢟ
ꢨ
ꢭ
ꢤ
ꢟ
ꢥ
ꢥ
ꢩ
ꢦ
ꢮ
Copyright 2000 − 2003, Texas Instruments Incorporated
ꢢ
ꢡ
ꢧ
ꢥ
ꢡ
ꢢ
ꢣ
ꢥ
ꢡ
ꢦ
ꢪ
ꢞ
ꢠ
ꢞ
ꢧ
ꢩ
ꢢ
ꢥ
ꢯ
ꢥ
ꢩ
ꢢ
ꢡ
ꢠ
ꢰ
ꢤ
ꢒ
ꢟ
ꢣ
ꢩ
ꢦ
ꢥ
ꢤ
ꢟ
ꢭ
ꢤ
ꢢ
ꢭ
ꢱ
ꢤ
ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ
ꢢ
ꢢ
ꢤ
ꢟ
ꢥ
ꢲ
ꢮ
ꢘ
ꢢ
ꢡ
ꢭ
ꢨ
ꢧ
ꢥ
ꢞ
ꢡ
ꢟ
ꢪ
ꢢ
ꢡ
ꢧ
ꢩ
ꢦ
ꢦ
ꢞ
ꢟ
ꢳ
ꢭ
ꢡ
ꢩ
ꢦ
ꢟ
ꢡ
ꢥ
ꢟ
ꢩ
ꢧ
ꢩ
ꢦ
ꢦ
ꢤ
ꢢ
ꢞ
ꢬ
ꢲ
ꢞ
ꢟ
ꢧ
ꢬ
ꢨ
ꢭ
ꢩ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265