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TLC3544

更新时间: 2024-11-25 21:53:39
品牌 Logo 应用领域
德州仪器 - TI 转换器输入元件
页数 文件大小 规格书
40页 784K
描述
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

TLC3544 数据手册

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TLC3544, TLC3548  
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL  
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS  
SLAS266C – OCTOBER 2000 – REVISED MAY 2003  
TLC3548  
DW OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
14-Bit Resolution  
Maximum Throughput 200 KSPS  
Analog Input Range 0-V to Reference  
Voltage  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
SCLK  
FS  
SDI  
CSTART  
AV  
2
DD  
Multiple Analog Inputs:  
– 8 Channels for TLC3548  
– 4 Channels for TLC3544  
3
AGND  
BGAP  
REFM  
REFP  
AGND  
4
EOC/INT  
SDO  
DGND  
5
D
D
D
D
Pseudodifferential Analog Inputs  
6
7
DV  
SPI/DSP-Compatible Serial Interfaces With  
SCLK up to 25 MHz  
DD  
8
CS  
A0  
A1  
A2  
A3  
AV  
DD  
9
A7  
A6  
A5  
A4  
Single 5-V Analog Supply; 3-/5-V Digital  
Supply  
10  
11  
12  
Low Power:  
– 4 mA (Internal Reference: 1.8 mA) for  
Normal Operation  
– 20 µA in Autopower-Down  
TLC3544  
DW OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Built-In 4-V Reference, Conversion Clock  
and 8x FIFO  
Hardware-Controlled and Programmable  
Sampling Period  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
SCLK  
FS  
SDI  
CSTART  
AV  
DD  
AGND  
BGAP  
REFM  
REFP  
AGND  
Programmable Autochannel Sweep and  
Repeat  
EOC/INT  
SDO  
DGND  
Hardware Default Configuration  
INL: ±1 LSB Max  
DV  
DD  
CS  
A0  
A1  
AV  
DNL: ±1 LSB Max  
SINAD: 80.8 dB  
DD  
A3  
A2  
THD: –95 dB  
description  
The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS  
analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V  
digital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serial  
input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS,  
slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The  
frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters  
connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual  
converter. CS can be tied to ground if only one converter is used. FS must be tied to DV  
if it is not used (such  
DD  
as in an SPI interface). When SDI is tied to DV , the device is set in hardware default mode after power-on,  
DD  
and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS)  
are needed to interface with the host.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000 – 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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