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TLC2551ID PDF预览

TLC2551ID

更新时间: 2024-11-22 22:53:03
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
23页 366K
描述
5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

TLC2551ID 数据手册

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TLC2551, TLC2552, TLC2555  
5 V, LOW POWER, 12-BIT, 400 KSPS,  
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN  
SLAS276 –MARCH 2000  
Maximum Throughput . . . 400 KSPS  
INL/DNL: ±1 LSB Max, SINAD: 72 dB,  
f = 20 kHz, SFDR: 85 dB, f = 20 kHz  
– TLC2552 – Dual Channels With  
Autosweep  
– TLC2555 – Single Channel With  
Pseudo-Differential Input  
i
i
SPI/DSP-Compatible Serial Interfaces With  
SCLK up to 20 MHz  
Optimized DSP Mode – Requires FS Only  
Low Power With Autopower Down  
– Operating Current : 3.5 mA  
Autopower Down: 8 µA  
Single 5 V Supply  
Rail-to-Rail Analog Input With 500 kHz BW  
Three Options Available:  
– TLC2551 – Single Channel Input  
Small 8-Pin MSOP and SOIC Packages  
PACKAGE TOP VIEW  
TLC2551  
TLC2552  
TLC2555  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SDO  
FS  
CS/FS  
SDO  
CS/FS  
SDO  
V
V
SCLK  
V
SCLK  
REF  
REF  
REF  
GND  
AIN  
V
GND  
AIN0  
V
GND  
V
DD  
DD  
DD  
SCLK  
AIN1  
AIN(+)  
AIN(–)  
description  
The TLC2551/2552/2555 are a family of high performance, 12-bit, low power, miniature 1.5 µs, CMOS  
analog-to-digital converters (ADC). The TLC255x family uses a 5 V supply. Devices are available with single,  
dual, or single pseudo-differential inputs. The TLC2551 has a 3-state output chip select (CS), serial output clock  
(SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular  
host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate  
the start of a serial data frame. The TLV2552/55 have a shared CS/FS terminal.  
TLC2551/2/5 are designed to operate with very low power consumption. The power saving feature is further  
enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host  
processors with SCLK up to 20 MHz. TLC255x family uses the SCLK as the conversion clock, thus providing  
synchronous operation allowing a minimum conversion time of 1.5 µs using 20 MHz SCLK.  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
T
A
8-MSOP  
(DGK)  
8-SOIC  
(D)  
TLC2551CDGK  
TLC2552CDGK  
TLC2555CDGK  
TLC2551IDGK  
TLC2552IDGK  
TLC2555IDGK  
0°C to 70°C  
TLC2551ID  
TLC2552ID  
TLC2555ID  
40°C to 85°C  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

TLC2551ID 替代型号

型号 品牌 替代类型 描述 数据表
TLC2551IDR TI

完全替代

12 位 400kSPS ADC,串行输出、TMS320 兼容(最高 10MHz)和单通道
TLC2551IDGK TI

完全替代

5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

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TLC2552IDG4 TI

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