TL7702B, TL7705B, TL7733B
SUPPLY-VOLTAGE SUPERVISORS
The TL7705BM is obsolete
and no longer is supplied.
SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003
APPLICATION INFORMATION
V
S
System Supply
8
10 kΩ
V
CC
RESET
7
2
5
6
To System
RESET
SENSE
Reset Input
(from system)
RESIN
REF
CT
1
3
R
T
To System
RESET
RESET
GND
(see text)
10 kΩ
C
0.1 µF
4
T
Figure 8. System Reset Controller With Undervoltage Sensing
When the TL770xB SENSE terminal is used to monitor V , a current-limiting resistor in series with C is
CC
T
recommended. During normal operation, the timing capacitor is charged by the onboard current source to
approximately V or an internal voltage clamp (≈7.1-V Zener), whichever is less. When the circuit then is subjected
CC
to an undervoltage condition during which V
is rapidly slewed down, the voltage on CT exceeds that on V . This
CC
CC
forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when V
drops
CC
below V
, not when V
falls below V
.
(CT)
SENSE
T–
Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into
the CT terminal. Adding the external resistor, R , prevents false triggering. Its value is calculated as follows:
T
V(
VT
–
)
CT
RT
Where:
V
V
R
= V
or 7.1 V, whichever is less
(CT)
T–
T
CC
= 4.55 V (nom)
= value of series resistor required
For V
= 5 V:
CC
5
4.55
RT
1 mA
Therefore,
RT
450
Using a 20%-tolerance resistor, R should be greater than 560 Ω.
T
Adding this series resistor changes the duration of the reset pulse by no more than 10%. R extends the discharge
T
of C , but also skews the V
threshold. These effects tend to cancel one another. The precise percentage change
T
(CT)
can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration
of the supply-voltage fault condition.
Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used.
This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an
undefined state or delay system reset.
9
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