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TJA1463ATK PDF预览

TJA1463ATK

更新时间: 2024-11-26 02:52:51
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
37页 425K
描述
CAN FD signal improvement transceiver with Sleep mode

TJA1463ATK 数据手册

 浏览型号TJA1463ATK的Datasheet PDF文件第2页浏览型号TJA1463ATK的Datasheet PDF文件第3页浏览型号TJA1463ATK的Datasheet PDF文件第4页浏览型号TJA1463ATK的Datasheet PDF文件第5页浏览型号TJA1463ATK的Datasheet PDF文件第6页浏览型号TJA1463ATK的Datasheet PDF文件第7页 
TJA1463  
CAN FD signal improvement transceiver with Sleep mode  
Rev. 1 — 12 August 2020  
Product data sheet  
1 General description  
The TJA1463 is a member of the TJA146x family of transceivers that provide an interface  
between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol  
controller and the physical two-wire CAN bus. TJA146x transceivers implement the CAN  
physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and  
are fully interoperable with high-speed Classical CAN and CAN FD transceivers.  
The TJA1463 includes CAN Signal Improvement Capability (SIC), as defined in  
CiA 601-4. CAN signal improvement significantly reduces signal ringing in a network,  
allowing reliable CAN FD communication to function in larger topologies. In addition, the  
TJA1463 features a much tighter bit timing symmetry performance to enable CAN FD  
communication at 5 Mbit/s with a higher number of nodes and stub topologies. CAN FD  
operation at 8 Mbit/s and beyond is supported in point-to-point networks.  
The TJA1463 is intended as a simple replacement for high-speed Classical CAN and  
CAN FD transceivers, such as the TJA1043 from NXP. It offers pin compatibility and is  
designed to avoid changes to hardware and software design, allowing the TJA1463 to be  
easily retrofitted to existing applications.  
An AEC-Q100 Grade 0 variant, the TJR1463, is available for high temperature  
applications, supporting operation at 150 °C ambient temperature.  
2 Features and benefits  
2.1 General  
ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant  
Implements CAN Signal Improvement Capability as defined in CiA 601-4 to significantly  
reduce signal ringing effects in a network  
Much tighter bit timing symmetry performance allowing more time to reduce signal  
ringing  
Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)  
Qualified according to AEC-Q100 Grade 1  
VIO input for interfacing with 3.3 V to 5 V microcontrollers  
Listen-only mode for node diagnosis and failure containment  
Available in SO14 and leadless HVSON14 (3.0 mm x 4.5 mm) packages; HVSON14  
with improved Automated Optical Inspection (AOI) capability.  
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)  
compliant)  
2.2 Predictable and fail-safe behavior  
Undervoltage detection with defined handling on all supply pins  
 
 
 
 

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