Datasheet > TDOTG1120-00BC

TDOTG1120-00BC

更新时间： 2024-02-22 03:40:21

品牌	Logo	应用领域
PLX		/
页数	文件大小	规格书
12页	403K
描述
Micro Peripheral IC,

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技术参数
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TDOTG1120-00BC 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.1
Base Number Matches：	1

TDOTG1120-00BC 数据手册

Data Sheet

TransDimension

TD1120

GPIO

V_DDW

General Purpose IO.

The state of this pin is used to indicate whether a 12MHz or a

30MHz Crystal/Oscillator is being used.

CLKCFG

V_DD3.3

CLKCFG

Frequency

12 MHz Crystal

12 MHz 3.3V Oscillator input on OSC1

30 MHz Crystal

30 MHz 3.3V Oscillator input on OSC1

V_DD3.3

Data lines for USB Peripheral Port, which may serve as an OTG

port in combination with Host Port 1. If not used, these two pins

should be left floating.

DM_P, DP_P

DM₁, DP₁

DM₂, DP₂

Data lines for Host Port 1, which may serve as a USB Host or an

OTG port in combination with the Peripheral Port. If not used, these

two pins should be left floating.

Data lines for Host Port 2, a dedicated USB Host port. If not used,

these two pins should be left floating.

/PO

/OC

V_DD3.3

Turn on/off the gang power for all Host ports.

Over current condition indicator for gang powered Host ports.

Connected to the ID pin of the mini-AB connector for OTG applications. With the

help of an internal pull-up resistor, it determines the chip’s responsibility in an OTG

application, (0: A-DEVICE, 1: B-DEVICE).

V_DD3.3

For non-OTG application, this pin should be left floating.

Turn on/off the external V_BUS(5V) for OTG operation (1: V_BUSoff; 0: V_BUSon) when

using the external Chargepump.

V_DD3.3

/EXVBO

VBUS

V_BUSinput used by the Peripheral port for connection; and also

sampled during HNP/SRP operations when used as an OTG port.

This pin should be left floating in a Host only application.

V_BUSpulsing control. This pin is used only OTG port is operating as

a B-DEVICE.

VBP

V_DD3.3

EXT

V_DD3.3AInternal Chargepump output for N-MOSFET (Refer Section TBD)

PD_PMOS

V_DD3.3AInternal Chargepump output for P-MOSFET (optional switch on the

VOUT)

VOUT

R_REF

Internal Chargepump output voltage feedback pin

V_DD3.3A

Connect external reference resistor (12 kΩ ± 1%) to V_SSA

ENVREG

V_DD3.3AEnables the internal Voltage Regulator if asserted. If not used, this

pin should be tied to V_SS.

VREGOUT

Internal Voltage Regulator output of 2.5V

If enabled, this output should be connected to the V_DD2.5, V_DD2.5A

(and V_DDWif Wide-range IO is at 2.5V) supplies of the chip.

If the Regulator is disabled, then this pin should be treated as

another V_DD2.5supply input to the chip.

XMODE

TEST

V_DD3.3

V_DDW

This pin should be grounded for normal operation.

Factory test mode. This pin should be grounded or left floating (has

an internal pull-down) for normal operation.

ATEST13

V_DDW

Additional address pin for debug usage. Should be grounded or left

TransDimension Inc. — Proprietary

1...4 5 678 9 10...12

中文翻译

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