Datasheet > TDOTG1120-00BC

TDOTG1120-00BC

更新时间： 2024-01-14 13:31:39

品牌	Logo	应用领域
PLX		/
页数	文件大小	规格书
12页	403K
描述
Micro Peripheral IC,

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技术参数
数据手册

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TDOTG1120-00BC 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.1
Base Number Matches：	1

TDOTG1120-00BC 数据手册

TransDimension

TD1120

Data Sheet

A10

B10

C10

D10

E10

F10

G10

H10

J10

K10

TD1120

A B C D E F G H J K

Figure 5 - TD1120 84-ball BGA 7x7mm package (top views)

Pin Definitions

The following notations are used to indicate the type of a signal/pin:

INPUT

OUTPUT

ACTIVE LEVEL PROGRAMMABLE

BI-DIRECTIONAL

POWER/GROUND

ACTIVE HIGH

WIRED OR

PASSIVE

NOT APPLICABLE

NO CONNECT

ACTIVE LOW

Pin/Signal

Signal Active Voltage

Level

Pin/Signal

Name

Type

Level

Description

OSC₁

V_DD3.3AA 12 MHz or 30 MHz passive crystal should be connected across

the two pins. Optionally, a 12 MHz or 30 MHz Oscillator can be

sourced through OSC1 while keeping OSC2 unconnected.

OSC₂

/RESET

/CS

V_DDW

Hardware reset.

Chip select.

/WR

Write strobe.

/RD

Read strobe.

A₁₂:A₁

Address bus for direct address space of 8K bytes.

16-bit data bus.

D₁₅:D₀

DRQ₁:DRQ₀

ACK₁:ACK₀

EOT₁:EOT₀

DMA Request outputs to support 2 channels

DMA Acknowledge

Optional DMA End Of Transfer indicator

Interrupt to the MCU. This pin can be software configured as a

regular output or WO. (WO is the default).

INT¹

O/WO

V_DDW

The active level for INT is programmable by software but defaults to active low after power on or hardware reset. This feature allows glue-less interfacing

with most microprocessors. Caution must be taken in user software to make sure relevant operations (interrupt) are disabled before alterations to default active

levels are made.

TransDimension Inc. — Proprietary

1...3 4 567 8 9...12

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