TC74LCX74FT

更新时间： 2024-11-10 21:58:47

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器
页数	文件大小	规格书
9页	175K
描述
Low-Voltage Dual D-Type Flip-Flop with 5-V Tolerant Inputs and Outputs

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中文翻译

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数据手册

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TC74LCX74FT 数据手册

TC74LCX74F/FN/FT

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74LCX74F,TC74LCX74FN,TC74LCX74FT

Low-Voltage Dual D-Type Flip-Flop with 5-V Tolerant Inputs and Outputs

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74LCX74F/FN/FT is a high-performance CMOS D-type

flip-flop. Designed for use in 3.3-V systems, it achieves

TC74LCX74F

high-speed operation while maintaining the CMOS low power

dissipation.

The device is designed for low-voltage (3.3 V) V

applications,

but it could be used to interface to 5-V supply environment for

inputs.

The signal level applied to the D input is transferred to Q

output during the positive going transition of the CK pulse. CLR

and PR are independent of the CK and are accomplished by

setting the appropriate input low.

All inputs are equipped with protection circuits against static

discharge.

TC74LCX74FN

Features

Low-voltage operation: V = 2.0 to 3.6 V

High-speed operation: t = 7.0 ns (max) (V

= 3.0 to 3.6 V)

= 24 mA (min) (V = 3.0 V)

pd CC

Output current: |I |/I

OH OL CC

Latch-up performance: ±500 mA

Available in JEDEC SOP, JEITA SOP and TSSOP

Power-down protection provided on all inputs and outputs

Pin and function compatible with the 74 series

(74AC/VHC/HC/F/ALS/LS etc.) 74 type

TC74LCX74FT

Weight

SOP14-P-300-1.27: 0.18 g (typ.)

SOL14-P-150-1.27: 0.12 g (typ.)

TSSOP14-P-0044-0.65: 0.06 g (typ.)

2002-01-11

12 3 4 5 6 7...9

中文翻译

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