Datasheet > TC74HC4020AP_07

TC74HC4020AP_07

更新时间： 2024-11-16 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		/
页数	文件大小	规格书
10页	465K
描述
CMOS Digital Integrated Circuit Silicon Monolithic

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中文翻译

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数据手册

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TC74HC4020AP_07 数据手册

TC74HC4020,4040AP/AF/AFN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC4020AP,TC74HC4020AF,TC74HC4020AFN

TC74HC4040AP,TC74HC4040AF,TC74HC4040AFN

TC74HC4020AP/AF/AFN 14-Stage Binary Counter

TC74HC4040AP/AF/AFN 12-Stage Binary

Note: xxxFN (JEDEC SOP) is not available in

Counter

Japan.

TC74HC4020AP, TC74HC4040AP

The TC74HC4020A/TC74HC4040A are high speed CMOS

BINARY COUNTER/DIVIDERs fabricated with silicon gate

C²MOS technology.

They achieve the high speed operetion similar to equivalent

LSTTL while maintaining the CMOS dissipation.

The TC74HC4020A is a 14-STAGE BINARY COUNTER, and

the TC74HC4040A is a 12-STAGE BINARY COUNTER.

Setting CLR to high resets the counter to low.

A negative transition on the CK input brings one increment

into the counter.

TC74HC4020AF, TC74HC4040AF

The TC74HC4020A provides 12 divided outputs: 1’st stage and

stage 4 thru stage 14. At Q14, a 1/16384 divided frequency will

be output.

The TC74HC4040A provides all divided output stages, and at

Q12, a 1/4096 divided frequency will be output.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC4020AFN, TC74HC4040AFN

Features

•

High speed: f

= 73 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

Weight

Wide operating voltage range: V

(opr) = 2~6 V

DIP16-P-300-2.54A

SOP16-P-300-1.27A

SOL16-P-150-1.27

: 1.00 g (typ.)

: 0.18 g (typ.)

: 0.13 g (typ.)

Pin and function compatible with 4020B/4040B

2007-10-01

12 3 4 5 6 7...10

中文翻译

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