Datasheet > TC74HC4024AP_07

TC74HC4024AP_07

更新时间： 2024-09-30 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		计数器
页数	文件大小	规格书
8页	270K
描述
CMOS Digital Integrated Circuit Silicon Monolithic 7-Stage Binary Counter

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数据手册

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TC74HC4024AP_07 数据手册

TC74HC4024AP/AF

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC4024AP,TC74HC4024AF

7-Stage Binary Counter

The TC74HC4024A is a high speed CMOS 7-STAGE BINARY

COUNTER fabricated with silicon gate C²MOS technology.

TC74HC4024AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

A negative transition on the CK input brings one increment

to the counter.

A CLR input is used to reset the counter to the all low level

state. A high level at CLR accomplishes the reset function.

All divided output stages are provided, and the last stage,

1/128 divided frequency will be obtained.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC4024AF

Features

•

High speed: f

= 70 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

Weight

DIP14-P-300-2.54

SOP14-P-300-1.27A

∼

−

Balanced propagation delays: t

pHL

pLH

: 0.96 g (typ.)

: 0.18 g (typ.)

Wide operating voltage range: V

(opr) = 2~6 V

Pin and function compatible with 4024B

Pin Assignment

2007-10-01

12 3 4 5 6 7 8

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