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TC74HC221AP_07 PDF预览

TC74HC221AP_07

更新时间: 2024-11-02 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA 振荡器
页数 文件大小 规格书
13页 479K
描述
Dual Monostable Multivibrator

TC74HC221AP_07 数据手册

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TC74HC221AP/AF/AFN  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC221AP,TC74HC221AF,TC74HC221AFN  
Dual Monostable Multivibrator  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74HC221A is a high speed CMOS MONOSTABLE  
MULTIVIBRATOR fabricated with silicon gate C2MOS  
TC74HC221AP  
technology.  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
There are two trigger inputs, A input (negative edge), and B  
input (positive edge). These inputs are valid for a slow rise/fall  
time signal (tr = tf = 1 s) as they are schmitt trigger inputs. This  
device may also be triggered by using CLR input (positive  
edge).  
After triggering, the output stays in a MONOSTABLE state for  
a time period determined by the external resistor and capacitor  
TC74HC221AF  
(Rx, Cx ). A low level at the CLR input breaks this state.  
Limits for Cx and Rx are:  
External capacitor, Cx: No limit  
External resistor, Rx: V  
V
= 2.0 V more than 5 kΩ  
3.0 V more than 1 kΩ  
CC  
CC  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
TC74HC221AFN  
Features (Note)  
High speed: t = 25 ns (typ.) at V  
= 5 V  
CC  
pd  
Low power dissipation  
Standy by State: I  
= 4 μA (max) at Ta = 25°C  
CC  
Active State: I  
= 700 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 10 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 4 mA (min)  
OL  
OH  
Weight  
Balanced propagation delays: t  
t
pHL  
pLH  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
Pin and function compatible with 74LS221  
Note: In the case of using only one circuit, CLR should be  
tied to GND, Rx/CxCxQQ should be tied to OPEN, the other inputs should be tied to V  
or GND.  
CC  
1
2007-10-01  

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