Datasheet > TC74HC237AP_07

TC74HC237AP_07

更新时间： 2024-11-28 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		锁存器
页数	文件大小	规格书
9页	384K
描述
3-to-8 Line Decoder/Latch

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中文翻译

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数据手册

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TC74HC237AP_07 数据手册

TC74HC237AP/AF

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC237AP,TC74HC237AF

3-to-8 Line Decoder/Latch

The TC74HC237A is a high speed CMOS 3-to-8 LINE

DECODER ADDRESS LATCH fabricated with silicon gate

C2MOS technology.

TC74HC237AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

It is composed of a 3-bit input latches with a common GL

enable input and 3-to-8 line decoder with enable inputs G1 and

G2 . The 3-bit binary data is stored into the input latch on the

high level of GL . The value of this data determines which one of

the outputs will go low.

When the enable input G1 is held low or G2 is held high,

decoding function is inhibited and all the 8 outputs go high. The

two enable inputs are provided to ease cascade connection and

permits the application address decoder for memory system.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC237AF

Features

•

High speed: t = 12 ns (typ.) at V

= 5 V

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

Weight

DIP16-P-300-2.54A

SOP16-P-300-1.27A

: 1.00 g (typ.)

: 0.18 g (typ.)

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

Wide operating voltage range: V

(opr) = 2~6 V

Pin and function compatible with 74LS237

Pin Assignment

2007-10-01

12 3 4 5 6 7...9

中文翻译

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TC74HC238AF(F)	TOSHIBA	获取价格	TC74HC238AF(F)
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