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TC74HC173AP_07 PDF预览

TC74HC173AP_07

更新时间: 2024-11-18 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
9页 306K
描述
Quad D-Type Register (3-state)

TC74HC173AP_07 数据手册

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TC74HC173AP/AF  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC173AP,TC74HC173AF  
Quad D-Type Register (3-state)  
The TC74HC173A is a high speed CMOS D-TYPE REGISTER  
fabricated with silicon gate C2MOS technology.  
TC74HC173AP  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
It consists a 4-bit register consisting of D-type flip-flops and  
3-state buffers. The four flip-flops are controlled by a common  
clock input (CK) and a common clear input (CLR).  
Signals applied to the data inputs (D1~D4) are stored in the  
respective flip-flops on the positive going transition of CK when  
clock control inputs (G1, G2) are held low.  
The clear function is asynchronous to CK and active on a high  
level. The stored data are enabled to each outputs when output  
control inputs (M, N) are held low, else the outputs are high  
impedance state.  
TC74HC173AF  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
High speed: f  
= 47 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 15 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 6 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2~6 V  
CC  
Pin and function compatible with 74LS173  
Pin Assignment  
1
2007-10-01  

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