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TC74HC161AP_07 PDF预览

TC74HC161AP_07

更新时间: 2024-11-14 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
15页 644K
描述
Binary, Synchronous Clear

TC74HC161AP_07 数据手册

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TC74HC161,163AP/AF/AFN  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC161AP,TC74HC161AF,TC74HC161AFN  
TC74HC163AP,TC74HC163AF,TC74HC163AFN  
Synchronous Presettable 4-Bit Counter  
TC74HC161AP/AF/AFN Binary, Asynchronous  
Clear  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
TC74HC163AP/AF/AFN Binary, Synchronous  
Clear  
TC74HC161AP, TC74HC163AP  
TC74HC161AF, TC74HC163AF  
TC74HC161AFN, TC74HC163AFN  
The TC74HC161A and 163A are high speed CMOS BINARY  
PRESETTABLE COUNTERs fabricated with silicon gate C2MOS  
technology.  
They achieve the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
The CK input is active on the rising edge. Both LOAD and  
CLR inputs are active on low logic level.  
Presetting of their IC’s is synchronous to the rising edge of CK.  
The clear function of the TC74HC163A is synchronous to CK,  
while the TC74HC161A is cleared asynchronously.  
Two enable inputs (ENP and ENT) and CO are provided to  
enable easy cascading of counters, which facilitates easy  
implementation of n-bit counters without using external gates.  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
High speed: f  
= 63 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 10 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 4 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Weight  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
Pin and function compatible with 74LS161, 163  
Pin Assignment  
1
2007-10-01  

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