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TC74HC112AP(F) PDF预览

TC74HC112AP(F)

更新时间: 2024-11-16 21:15:55
品牌 Logo 应用领域
东芝 - TOSHIBA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
9页 224K
描述
IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,PLASTIC

TC74HC112AP(F) 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.84JESD-30 代码:R-PDIP-T16
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
最大频率@ Nom-Sup:24000000 Hz最大I(ol):0.004 A
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
电源:2/6 V认证状态:Not Qualified
子类别:FF/Latches表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
Base Number Matches:1

TC74HC112AP(F) 数据手册

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TC74HC112AP/AF  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC112AP,TC74HC112AF  
Dual J-K Flip Flop with Preset and Clear  
The TC74HC112A is a high speed CMOS DUAL J-K FLIP  
FLOP fabricated with silicon gate C2MOS technology.  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
In accordance with the logic levels applied to the J and K  
inputs, the outputs change state on the negative going transition  
of the clock pulse.  
TC74HC112AP  
CLR and PR are independent of the clock and are actived  
by a low logic level on the corresponding input.  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
TC74HC112AF  
Features  
High speed: f  
= 67 MHz (typ.) at V  
= 5 V  
max  
CC  
Low power dissipation: I  
= 2 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 10 LSTTL loads  
Symmetrical output impedance: |I | = I  
= 4 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
Pin and function compatible with 74LS112  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
Pin Assignment  
1
2012-02-29  

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