Datasheet > TC74HC112AP_07

TC74HC112AP_07

更新时间： 2024-09-28 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器
页数	文件大小	规格书
10页	312K
描述
Dual J-K Flip Flop with Preset and Clear

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中文翻译

获取价格

数据手册

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TC74HC112AP_07 数据手册

TC74HC112AP/AF/AFN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC112AP,TC74HC112AF,TC74HC112AFN

Dual J-K Flip Flop with Preset and Clear

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74HC112A is a high speed CMOS DUAL J-K FLIP

FLOP fabricated with silicon gate C²MOS technology.

TC74HC112AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

In accordance with the logic levels applied to the J and K

inputs, the outputs change state on the negative going transition

of the clock pulse.

CLR and PR are independent of the clock and are actived

by a low logic level on the corresponding input.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC112AF

Features

•

High speed: f

= 67 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 2 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

TC74HC112AFN

Wide operating voltage range: V

(opr) = 2 to 6 V

Pin and function compatible with 74LS112

Pin Assignment

Weight

DIP16-P-300-2.54A

SOP16-P-300-1.27A

SOL16-P-150-1.27

: 1.00 g (typ.)

: 0.18 g (typ.)

: 0.13 g (typ.)

2007-10-01

12 3 4 5 6 7...10

中文翻译

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TC74HC11AF_07	TOSHIBA	获取价格	CMOS Digital Integrated Circuit Silicon Monolithic Triple 3-Input AND Gate
TC74HC11AFN	TOSHIBA	获取价格	TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC74HC11AFN-ELP	TOSHIBA	获取价格	IC HC/UH SERIES, TRIPLE 3-INPUT AND GATE, PDSO14, 0.150 INCH, PLASTIC, SOIC-14, Gate