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SY89871UMG

更新时间： 2024-01-31 01:45:21
品牌 Logo 应用领域
麦瑞 - MICREL 时钟
页数 文件大小 规格书
10页 158K
描述
2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER

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SY89871UMG 数据手册

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®  
2.5GHz ANY DIFF. IN-TO-LVPECL  
PROGRAMMABLE CLOCK DIVIDER/  
FANOUT BUFFER W/INTERNAL TERMINATION  
®
Precision Edge  
SY89871U  
FEATURES  
®
Precision Edge  
„ Two matched-delay outputs:  
• Bank A: undivided pass-through (QA)  
• Bank B: programmable divide by  
2, 4, 8, 16 (QB0, QB1)  
DESCRIPTION  
„ Matched delay: all outputs have matched delay,  
independent of divider setting  
The SY89871U is a 2.5V/3.3V LVPECL output precision  
clock divider capable of accepting a high-speed differential  
clock input (AC or DC-coupled) CML, LVPECL, HSTL or  
LVDS clock input signal and dividing down the frequency  
using a programmable divider ratio to create a frequency-  
locked lower speed version of the input clock (Bank B).  
Available divider ratios are 2, 4, 8 and 16. In a typical  
622MHz clock system this would provide availability of  
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock  
components.  
„ Guaranteed AC performance:  
• >2.5GHz f  
MAX  
• <250ps t /t  
r f  
• <670ps t (matched delay)  
pd  
• <15ps within-device skew  
„ Low jitter design  
• <1ps  
cycle-to-cycle jitter  
RMS  
• <10ps total jitter  
PP  
„ Power supply 3.3V or 2.5V  
The differential input buffer has a unique internal  
termination design that allows access to the termination  
network through a VT pin. This feature allows the device to  
„ Unique patent-pending input termination and VT pin  
for DC- and AC-coupled inputs: any differential  
inputs (LVPECL, LVDS, CML, HSTL)  
easily interface to different logic standards. A V  
REF-AC  
„ TTL/CMOS inputs for select and reset  
„ 100K EP compatible LVPECL outputs  
„ Parallel programming capability  
reference is included for AC-coupled applications.  
The SY89871U includes two phase-matched output  
banks. Bank A (QA) is a frequency-matched copy of the  
input. Bank B (QB0, QB1) is a divided down output of the  
input frequency. Bank A and Bank B maintain a matched  
delay independent of the divider setting.  
„ Wide operating temperature range: –40°C to +85°C  
®
„ Available in 16-pin (3mm x 3mm) MLF package  
All support documentation can be found on Micrel’s web  
site at: www.micrel.com.  
APPLICATIONS  
„ OC-3 to OC-192 SONET/SDH applications  
„ Transponders  
„ Oscillators  
„ SONET/SDH line cards  
FUNCTIONAL BLOCK DIAGRAM  
TYPICAL PERFORMANCE  
QA  
QA@622MHz and QB@155.5MHz  
/QA  
VREF-AC  
QA  
QB0  
622MHz  
Output  
IN  
Divided  
by  
2, 4, 8  
or 16  
/QB0  
50Ω  
VT  
/QA  
50Ω  
QB1  
/IN  
QB0  
/QB1  
S0  
S1  
155.5MHz  
Output  
÷4  
Decoder  
/QB0  
/RESET  
Precision Edge is a registered trademark of Micrel, Inc.  
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.  
Rev.: F  
Amendment: /0  
M9999-082407  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: August 2007  
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