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SY89874UMGTR

更新时间: 2024-09-12 04:30:07
品牌 Logo 应用领域
麦瑞 - MICREL 逻辑集成电路驱动时钟
页数 文件大小 规格书
10页 111K
描述
2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

SY89874UMGTR 数据手册

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®  
2.5GHz ANY DIFF. IN-TO-LVPECL  
PROGRAMMABLE CLOCK DIVIDER/  
®
Precision Edge  
SY89874U  
FANOUT BUFFER WITH INTERNAL TERMINATION  
FEATURES  
Integrated programmable clock divider and 1:2  
®
fanout buffer  
Precision Edge  
Guaranteed AC performance over temperature and  
voltage:  
• > 2.5GHz f  
DESCRIPTION  
MAX  
• < 250ps t /t  
• < 15ps within device skew  
This low-skew, low-jitter device is capable of accepting a  
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or  
HSTL clock input signal and dividing down the frequency  
using a programmable divider ratio to create a frequency-  
locked, lower speed version of the input clock. Available divider  
ratios are 2, 4, 8 and 16, or straight pass-through. In a typical  
622MHz clock system this would provide availability of  
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock  
components.  
r f  
Low jitter design:  
• < 10ps total jitter  
PP  
• < 1ps  
cycle-to-cycle jitter  
RMS  
Unique input termination and V pin for DC-coupled  
T
and AC-coupled Inputs; CML, PECL, LVDS and  
HSTL  
TTL/CMOS inputs for select and reset  
100k EP compatible LVPECL outputs  
Parallel programming capability  
Programmable divider ratios of 1, 2, 4, 8 and 16  
Low voltage operation 2.5V or 3.3V  
Output disable function  
The differential input buffer has a unique internal termination  
design that allows access to the termination network through  
a V pin. This feature allows the device to easily interface to  
T
different logic standards. A V  
AC-coupled applications.  
reference is included for  
REF-AC  
The /RESET input asynchronously resets the divider. In  
the pass-through function (divide by 1) the /RESET  
synchronously enables or disables the outputs on the next  
falling edge of IN (rising edge of /N).  
–40°C to 85°C temperature range  
®
Available in 16-pin (3mm × 3mm) MLF package  
TYPICAL PERFORMANCE  
APPLICATIONS  
SONET/SDH line cards  
Transponders  
OC-12 to OC-3  
Translator/Divider  
High-end, multiprocessor sensors  
FUNCTIONAL BLOCK DIAGRAM  
LVDS  
622MHz  
Clock In  
LVPECL  
155.5MHz  
Clock Out  
Divide-by-4  
S2  
/RESET  
Enable  
FF  
622MHz In  
Enable  
MUX  
Q0  
IN  
/Q0  
MUX  
Q1  
IN  
VT  
Divided  
by  
2, 4, 8  
or 16  
R0  
R1  
/Q1  
/IN  
Q0  
/IN  
S0  
155.5MHz Out  
Decoder  
S1  
VREF-AC  
/Q0  
Precision Edge is a registered trademark of Micrel, Inc.  
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.  
Rev.: D  
Amendment: /0  
M9999-020707  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: February 2007  

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