Datasheet > SY89872U_0708

SY89872U_0708

更新时间： 2024-02-23 00:08:02

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
10页	173K
描述
2.5V, 2GHz ANY DIFF. IN-TO-LVDS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SY89872U_0708 数据手册

Precision Edge^®

2.5V, 2GHz ANY DIFF. IN-TO-LVDS

PROGRAMMABLE CLOCK DIVIDER/

FANOUT BUFFER W/INTERNAL TERMINATION

SY89872U

Micrel, Inc.

Precision Edge

SY89872U

FEATURES

Guaranteed AC performance over temperature and

Precision Edge

voltage:

• >2GHz f

MAX

• < 750ps t (matched delay between banks)

• < 15ps within-device skew

• < 200ps rise/fall time

DESCRIPTION

This 2.5V low-skew, low-jitter, precision LVDS output clock

divider accepts any high-speed differential clock input (AC

or DC-coupled) CML, LVPECL, HSTL or LVDS and divides

down the frequency using a programmable divider ratio to

create a frequency-locked, lower speed version of the input

clock. The SY89872U includes two output banks. Bank A is

an exact copy of the input clock (pass through) with matched

propagation delay to Bank B, the divided output bank.

Available divider ratios are 2, 4, 8 and 16. In a typical

622MHz clock system this would provide availability of

311MHz, 155MHz, 77MHz or 38MHz auxiliary clock

components.

Low jitter design

• < 1ps

cycle-to-cycle jitter

RMS

• < 10ps total jitter

Unique input termination and VT pin for DC-coupled

and AC-coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)

Precision differential LVDS outputs

Matched delay: all outputs have matched delay,

independent of divider setting

TTL/CMOS inputs for select and reset/disable

Two output banks (matched delay)

The differential input buffer has a unique internal

termination design that allows access to the termination

• Bank A: Buffered copy of input clock (undivided)

network through a V pin. This feature allows the device to

• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),

two copies

easily interface to different logic standards. A V

REF-AC

reference is included for AC-coupled applications.

2.5V power supply

The SY89872U is part of Micrel’s high-speed Precision

Wide operating temperature range: –40°C to +85°C

Edge timing and distribution family. For 3.3V applications,

Available in 16-pin (3mm x 3mm) MLF package

consider the SY89873L. For applications that require an

LVPECL output, consider the SY89872U.

APPLICATIONS

The /RESET input asynchronously resets the divider

outputs (Bank B). In the pass-through function (Bank A) the

/RESET synchronously enables or disables the outputs on

the next falling edge of IN (rising edge of /IN). Refer to the

“Timing Diagram.”

OC-3 to OC-192 SONET/SDH applications

Transponders

Oscillators

SONET/SDH line cards

FUNCTIONAL BLOCK DIAGRAM

TYPICAL APPLICATION

/RESET,

Enable

622MHz/155.5MHz

SONET Clock Generator

/DISABLE

Enable

MUX

/QA

622MHz LVPECL

Clock In

622MHz LVDS

Clock Out

/QA

OC-12 or OC-3

Clock Generator

/IN

QB0

155.5MHz LVDS

Clock Out

Divided

/QB0

50Ω

2, 4, 8

/QB

V_T

50Ω

or 16

QB1

/IN

Bank A: 622MHz for OC-12 line card

Bank B: 155.5MHz for OC-3 line card (set to divide-by-4)

/QB1

V_REF-AC

Decoder

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Rev.: F

Amendment: /0

M9999-082407

hbwhelp@micrel.com or (408) 955-1690

Issue Date: August 2007

12 3 4 5 6 7...10

中文翻译

下载PDF

与SY89872U_0708相关器件

型号	品牌	获取价格	描述	数据表
SY89872UMG	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89872UMGTR	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89872UMI	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89872UMITR	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89873L	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873L	MICROCHIP	获取价格	This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed
SY89873L_0708	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
SY89873LMG	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873LMGTR	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873LMI	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER

与SY89872U_0708相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

28
AIC1781A 电池充电控制器深度解析
2024-09-03

17
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

58
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

64

产品中心

服务支持

精选活动

关于我们

帮助中心

SY89872U_0708

SY89872U_0708 数据手册

与SY89872U_0708相关器件

与SY89872U_0708相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SY89872U_0708

SY89872U_0708 数据手册

与SY89872U_0708相关器件

与SY89872U_0708相关文章

您还可以找

您在本页遇到什么问题？