SY89875U

更新时间： 2024-09-12 04:30:07

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
10页	231K
描述
2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1;2 FANOUT BUFFER W/ INTERNAL TERMINATION

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SY89875U 数据手册

2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS

PROGRAMMABLE CLOCK DIVIDER AND 1:2

FANOUT BUFFER W/ INTERNAL TERMINATION

Precision Edge™

SY89875U

FINAL

FEATURES

DESCRIPTION

I Integrated programmable clock divider and 1:2

This low-skew, low-jitter device is capable of accepting a

high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS

or HSTL clock input signal and dividing down the frequency

using a programmable divider to create a lower speed

version of the input clock. Available divider ratios are 2, 4, 8

and 16, or straight pass-through.

fanout buffer

I Guaranteed AC performance over temperature and

voltage:

• > 2.0GHz f

MAX

• < 200ps t /t

r f

• < 15ps within device skew

The differential input buffer has a unique internal

termination design that allows access to the termination

I Low jitter design:

network through a V pin. This feature allows the device to

• < 10ps (pk-pk) total jitter

• < 1ps (rms) cycle-to-cycle jitter

easily interface to different logic standards. A V

reference is included for AC-coupled applications.

REF-AC

I Unique input termination and V Pin for DC-coupled

The /RESET input asynchronously resets the divider. In

the pass-through function (divide by 1) the /RESET

synchronously enables or disables the outputs on the next

falling edge of IN (rising edge of /IN).

and AC-coupled Inputs; CML, PECL, LVDS and

HSTL

I LVDS compatible outputs

I TTL/CMOS inputs for select and reset

I Parallel programming capability

I Programmable divider ratios of 1, 2, 4, 8 and 16

I Low voltage operation 2.5V

I Output disable function

I –40°C to 85°C temperature range

I Available in 16-pin (3mm × 3mm) MLF™ package

TYPICAL PERFORMANCE

APPLICATIONS

OC-12 to OC-3

Translator/Divider

I SONET/SDH line cards

I Transponders

I High-end, multiprocessor servers

CML/LVPECL/LVDS

622MHz

LVDS

155.5MHz

Clock Out

Divide-by-4

Clock In

FUNCTIONAL BLOCK DIAGRAM

622MHz In

/IN

155.5MHz Out

/Q0

Precision Edge is a trademark of Micrel, Inc.

MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.

Rev.: A

Amendment: /1

Issue Date: February 2003

12 3 4 5 6 7...10

中文翻译

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与SY89875U相关器件

型号	品牌	获取价格	描述	数据表
SY89875U_07	MICREL	获取价格	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTE
SY89875U_0708	MICREL	获取价格	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS
SY89875UMG	MICREL	获取价格	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTE
SY89875UMG	MICROCHIP	获取价格	89875 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16
SY89875UMGTR	MICREL	获取价格	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTE
SY89875UMGTR	MICROCHIP	获取价格	89875 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16, 3 X 3
SY89875UMG-TR	MICROCHIP	获取价格	89875 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16
SY89875UMI	MICREL	获取价格	2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1;2 FANOUT BUFFER W/ INTE
SY89875UMI	MICROCHIP	获取价格	Low Skew Clock Driver, 89875 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, MLF
SY89875UMITR	MICROCHIP	获取价格	Low Skew Clock Driver, 89875 Series, 2 True Output(s), 0 Inverted Output(s), 3 X 3 MM, MLF

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