Datasheet > SY89873L

SY89873L

更新时间： 2024-02-12 19:39:54

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
11页	103K
描述
3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TERMINATION

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SY89873L 数据手册

Precision Edge^®

3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

PROGRAMMABLE CLOCK DIVIDER

FANOUT BUFFER W/ INTERNAL TERMINATION

SY89873L

Micrel, Inc.

Precision Edge

SY89873L

FEATURES

■ Guaranteed AC performance

Precision Edge

• > 2.0GHz f

output toggle

MAX

• > 3.0GHz f

input

MAX

DESCRIPTION

• < 800ps t (matched-delay between banks)

• < 15ps within-device skew

• < 190ps rise/fall time

This 3.3V low-skew, low-jitter, precision LVDS output clock

divider accepts any high-speed differential clock input (AC- or

DC-coupled) CML, LVPECL, HSTL or LVDS and divides down

the frequency using a programmable divider ratio to create a

frequency-locked, lower speed version of the input clock. The

SY89873L includes two output banks. Bank A is an exact

copy of the input clock (pass through) with matched

propagation delay to Bank B, the divided output bank. Available

divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock

system this would provide availability of 311MHz, 155MHz,

77MHz or 38MHz auxiliary clock components.

■ Low jitter design

• < 1ps

cycle-to-cycle jitter

RMS

• < 10ps total jitter

■ Unique input termination and V pin for DC-coupled

and AC-coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)

■ Precision differential LVDS outputs

■ Matched delay: all outputs have matched delay,

independent of divider setting

The differential input buffer has a unique internal termination

design that allows access to the termination network through

a VT pin. This feature allows the device to easily interface to

■ TTL/CMOS inputs for select and reset/disable

■ Two LVDS output banks (matched delay)

• Bank A: Buffered copy of input clock (undivided)

all AC- or DC-coupled differential logic standards. A V

REF-AC

• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),

reference is included for AC-coupled applications.

two copies

The SY89873L is part of Micrel’s high-speed Precision

■ 3.3V power supply

Edge timing and distribution family. For 2.5V applications,

consider the SY89872U. For applications that require an

LVPECL output, consider the SY89871U.

■ Wide operating temperature range: –40°C to +85°C

■ Available in 16-pin (3mm × 3mm) MLF package

The /RESET input asynchronously resets the divider outputs

(Bank B). In the pass-through function (Bank A) the /RESET

synchronously enables or disables the outputs on the next

falling edge of IN (rising edge of /N). Refer to the Timing

Diagram.

APPLICATIONS

■ SONET/SDH line cards

■ Transponders

All support documentation can be found on Micrel’s web

site at: www.micrel.com.

■ High-end, multiprocessor servers

FUNCTIONAL BLOCK DIAGRAM

TYPICAL APPLICATION

Enable

/RESET

622MHz/155.5MHz

SONET Clock Generator

Enable

MUX

V_REF-AC

/QA

622MHz LVDS

Clock Out

/QA

OC-12 or

OC-3

Clock Gen

622MHz LVPECL

Clock In

/IN

50Ω

QB0

QB 155.5MHz LVDS

/QB

Clock Out

V_T

Divided

2, 4, 8

or 16

/QB0

50Ω

/IN

QB1

Bank B: 155.5MHz: For OC-3 line card

Set to divide-by-4

/QB1

Bank A: 622MHz: For OC-12 line card

Set to pass-through

Decoder

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Rev.: F

Amendment: /0

M9999-020707

hbwhelp@micrel.com or (408) 955-1690

Issue Date: February 2007

12 3 4 5 6 7...11

中文翻译

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与SY89873L相关器件

型号	品牌	获取价格	描述	数据表
SY89873L_0708	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS
SY89873LMG	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873LMGTR	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873LMI	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89873LMITR	MICREL	获取价格	3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER FANOUT BUFFER W/ INTERNAL TER
SY89874AU	MICROCHIP	获取价格	This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS,
SY89874U	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMI
SY89874U	MICROCHIP	获取价格	This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or hig
SY89874U_07	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMI
SY89874U_08	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER

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