Datasheet > SY89871U

SY89871U

更新时间： 2023-12-06 20:09:10

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
13页	724K
描述
The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-spe

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SY89871U 数据手册

SY89871U

2.5GHz Any Diff. In-To-LVPECL

Programmable Clock Divider/Fanout Buffer

w/ Internal Termination

Precision Edge^®

General Description

Features

The SY89871U is a 2.5V/3.3V LVPECL output precision

clock divider capable of accepting a high-speed differential

clock input (AC or DC-coupled) CML, LVPECL, HSTL or

LVDS clock input signal and dividing down the frequency

using a programmable divider ratio to create a frequency-

locked lower speed version of the input clock (Bank B).

Available divider ratios are 2, 4, 8, and 16. In a typical

622MHz clock system this would provide availability of

311MHz, 115MHz, 77MHz, or 38MHz auxiliary clock

components.

 Two matched-delay outputs:

- Bank A: undivided pass-through (QA)

- Bank B: programmable divide by 2, 4, 8, 16 (QB0,

QB1)

 Matched delay: all outputs have matched delay,

independent of divider setting

 Guaranteed AC performance:

- >2.5GHz f_MAX

- <250ps t_r/t_f

The differential input buffer has a unique internal

termination design that allows access to the termination

network through a VT pin. This feature allows the device to

easily interface to different logic standards. A V_REF-AC

reference is included for AC-coupled applications.

- <670ps t_pd(matched delay)

- <15ps within-device skew

 Low jitter design

- 231fs RMS phase jitter (Typ)

 Power supply 3.3V or 2.5V

The SY89871U includes two phase-matched output banks.

Bank A (QA) is a frequency-matched copy of the input.

Bank B (QB0, QB1) is a divided down output of the input

frequency. Bank A and Bank B maintain a matched delay

independent of the divider setting.

 Unique patent-pending input termination and VT pin for

DC- and AC- coupled inputs: any differential inputs

(LVPECL, LVDS, CML, HSTL)

 TTL/CMOS inputs for select and reset

 100K EP compatible LVPECL outputs

 Parallel programming capability

Data sheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

 Wide operating temperature range: -40°C to +85°C

 Available in 16-pin (3mm x 3mm) QFN package

Typical Performance

Applications

 OC-3 to OC-192 SONET/SDH applications

 Transponders

 Oscillators

 SONET/SDH line cards

Precision Edge is a registered trademark of Micrel, Inc

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-010512-F

Oct. 1, 2013

hbwhelp@micrel.com or (408) 955-1690

12 3 4 5 6 7...13

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与SY89871U相关器件

型号	品牌	获取价格	描述	数据表
SY89871U_07	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER
SY89871UMG	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER
SY89871UMGTR	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER
SY89871UMI	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER
SY89871UMITR	MICREL	获取价格	2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER
SY89872U	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89872U	MICROCHIP	获取价格	This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed
SY89872U_0708	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS
SY89872UMG	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER
SY89872UMGTR	MICREL	获取价格	2.5V, 2GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TER

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