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SY89531LHH PDF预览

SY89531LHH

更新时间: 2024-11-11 02:54:43
品牌 Logo 应用领域
麦瑞 - MICREL 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
16页 105K
描述
3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND HSTL BUS CLOCK SYNTHESIZER

SY89531LHH 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTFQFP, TQFP64,.47SQ
针数:64Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.52Is Samacsys:N
JESD-30 代码:S-PQFP-G64JESD-609代码:e4
长度:10 mm湿度敏感等级:3
端子数量:64最高工作温度:85 °C
最低工作温度:最大输出时钟频率:622.08 MHz
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装等效代码:TQFP64,.47SQ封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8,3.3 V主时钟/晶体标称频率:18 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:295 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

SY89531LHH 数据手册

 浏览型号SY89531LHH的Datasheet PDF文件第2页浏览型号SY89531LHH的Datasheet PDF文件第3页浏览型号SY89531LHH的Datasheet PDF文件第4页浏览型号SY89531LHH的Datasheet PDF文件第5页浏览型号SY89531LHH的Datasheet PDF文件第6页浏览型号SY89531LHH的Datasheet PDF文件第7页 
®  
3.3V, PRECISION, 33MHz to 500MHz  
PROGRAMMABLE LVPECL AND HSTL BUS  
CLOCK SYNTHESIZER  
®
L  
Precision Edge  
SY89531L  
FEATURES  
Integrated synthesizer plus fanout buffers, clock  
®
Precision Edge  
drivers, and translator in a single 64-pin package  
3.3V ±10% power supply  
DESCRIPTION  
Low jitter: <50ps cycle-to-cycle  
Low pin-to-pin skew: <50ps  
The SY89531L programmable clock synthesizer/driver is  
part of a 3.3V, high-frequency, precision PLL-based clock  
synthesizer family optimized for multi-frequency, multi-  
processor server, enterprise networking and other computing  
applications that require the highest precision and integration.  
The device integrates the following blocks into a single  
monolithic IC:  
33MHz to 500MHz output frequency range  
Direct interface to crystal: 14MHz to 18MHz  
LVPECL/HSTL outputs  
TTL/CMOS compatible control logic  
3 independently programmable output frequency  
banks:  
• PLL (Phase-Lock-Loop)-based synthesizer  
• Fanout buffers  
• Clock generator (dividers)  
• 9 differential output pairs @BankB (HSTL)  
• 2 differential output pairs @BankA (LVPECL)  
• 2 differential output pairs @BankC (LVPECL)  
• Logic translation (LVPECL, HSTL)  
ExtVCO input allows synthesizer and crystal  
This level of integration minimizes the additive jitter and  
part-to-part skew associated with the discrete alternative,  
resulting in superior system-level timing as well as reduced  
board space and power. For applications that must interface  
to a reference clock, see the SY89536L.  
interface to be bypassed  
Available in 64-pin EPAD-TQFP  
Data sheets and support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
APPLICATIONS  
PRODUCT SELECTION GUIDE  
Servers  
Input  
Output  
Workstations  
Device  
Crystal Reference BankA  
BankB  
BankC  
Parallel processor-based systems  
Other high-performance computing  
Communications  
SY89531L  
SY89532L*  
SY89533L*  
SY89534L*  
SY89535L*  
SY89536L*  
X
X
X
LVPECL HSTL LVPECL  
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
LVPECL LVPECL LVPECL  
LVPECL LVDS LVPECL  
LVPECL HSTL LVPECL  
X
X
X
*Refer to individual data sheet for details.  
Precision Edge is a registered trademark of Micrel, Inc.  
Rev.: B  
Amendment: /0  
M9999-110405  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: October 2005  

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