Datasheet > SY10EP451L_0705

SY10EP451L_0705

更新时间： 2024-01-03 22:44:18

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
10页	439K
描述
3.3V ECL 6-Bit Differential Register with Master Reset

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SY10EP451L_0705 数据手册

SY10/100EP451L

3.3V ECL 6-Bit Differential Register

with Master Reset

General Description

Features

The SY10/100EP451L is a 6-bit fully differential register

with common clock and single-ended Master Reset (MR).

It is ideal for very high frequency applications where a

registered data path is necessary.

• 450ps typical propagation delay

• Maximum frequency > 3.0GHz typical

• Asynchronous Master Reset

• 20ps skew within device, 35ps skew device-to-device

• PECL mode operating range:

– V_CC= 3.0V to 3.6V with V_EE= 0V

• NECL mode operating range:

– V_CC= 0V with V_EE= –3.0V to –3.6V

• Open input default state

All inputs have an internal 75kΩ pull-down resistor.

Differential inputs have an override clamp. Unused

differential register inputs can be left open and will default

LOW. When the differential inputs are forced to a value

smaller than V_EE+1.2V, the clamp will override and force

the output to a default state.

The positive transition of CLK (pin 4) will latch the

registers. Master Reset (MR) HIGH will asynchronously

reset all registers forcing Q outputs to go LOW.

• Safety clamp on inputs

• Available in 32-pin TQFP

Applications

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

• High Speed Logic

• Wireless Communication Systems

• Data Communication Systems

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-051807-B

May 2007

hbwhelp@micrel.com or (408) 955-1690

12 3 4 5 6 7...10

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