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SY10EP51VZCTR PDF预览

SY10EP51VZCTR

更新时间: 2024-01-21 21:45:10
品牌 Logo 应用领域
麦瑞 - MICREL 触发器时钟
页数 文件大小 规格书
7页 498K
描述
5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK

SY10EP51VZCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.42
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列:10EJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.93 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:3000000000 Hz
湿度敏感等级:1位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):40 mA
Prop。Delay @ Nom-Sup:0.42 ns传播延迟(tpd):0.37 ns
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.94 mm
最小 fmax:3000 MHzBase Number Matches:1

SY10EP51VZCTR 数据手册

 浏览型号SY10EP51VZCTR的Datasheet PDF文件第2页浏览型号SY10EP51VZCTR的Datasheet PDF文件第3页浏览型号SY10EP51VZCTR的Datasheet PDF文件第4页浏览型号SY10EP51VZCTR的Datasheet PDF文件第5页浏览型号SY10EP51VZCTR的Datasheet PDF文件第6页浏览型号SY10EP51VZCTR的Datasheet PDF文件第7页 
5V/3.3V D FLIP-FLOP WITH RESET  
AND DIFFERENTIAL CLOCK  
ECL Pro™  
SY10EP51V  
FEATURES  
3.3V and 5V power supply options  
320ps typical propagation delay  
Maximum frequency > 3GHz typical  
75internal input pulldown resistor  
Transistor count: 143  
ECL Pro™  
DESCRIPTION  
Available in 8-Pin (3mm) MSOP and SOIC packages  
The SY10EP51V is a D flip-flop with reset and  
differential clock. The device is pin and functionally  
equivalent to the EL51 device.  
The reset input is an asynchronous, level triggered  
signal. Data enters the master portion of the flip-flop  
when CLK is LOW and is transferred to the slave, and  
thus the outputs, upon a positive transition of the CLK.  
The differential clock inputs of the EP51V allow the device  
to be used as a negative edge triggered flip-flop.  
The differential input employs clamp circuitry to  
maintain stability under open input conditions. When left  
open, the CLK input will be pulled down to V  
/CLK input will be biased a V /2.  
and the  
EE  
CC  
PIN NAMES  
TRUTH TABLE  
D
L
RESET  
CLK  
Z
Q
Pin  
CLK, /CLK  
RESET  
D
Function  
ECL Clock Inputs  
L
L
L
H
L
H
X
Z
ECL Asynchronous Reset  
ECL Data Input  
H
X
Z = LOW to HIGH Transition  
Q, /Q  
ECL Data Outputs  
Positive Supply  
VCC  
VEE  
Negative, 0 Supply  
ECL Pro is a trademark of Micrel, Inc.  
Rev.: D  
Amendment: /0  
M9999-112805  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: November2005  

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