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SY10EP52VZC PDF预览

SY10EP52VZC

更新时间: 2024-01-10 21:52:48
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
7页 112K
描述
5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP

SY10EP52VZC 技术参数

是否Rohs认证:不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N其他特性:NECL MODE OPERATING RANGE: VCC=0V, VEE=-3.3V TO -5.5V
系列:10EJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.93 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:4000000000 Hz
湿度敏感等级:1位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):47 mA
Prop。Delay @ Nom-Sup:0.41 ns传播延迟(tpd):0.38 ns
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:FF/Latches最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:NEGATIVE EDGE宽度:3.94 mm
最小 fmax:4000 MHzBase Number Matches:1

SY10EP52VZC 数据手册

 浏览型号SY10EP52VZC的Datasheet PDF文件第2页浏览型号SY10EP52VZC的Datasheet PDF文件第3页浏览型号SY10EP52VZC的Datasheet PDF文件第4页浏览型号SY10EP52VZC的Datasheet PDF文件第5页浏览型号SY10EP52VZC的Datasheet PDF文件第6页浏览型号SY10EP52VZC的Datasheet PDF文件第7页 
5V/3.3V DIFFERENTIAL DATA  
AND CLOCK D FLIP-FLOP  
ECL Pro™  
SY10EP52V  
FEATURES  
Guaranteed maximum frequency >4GHz  
Guaranteed <410ps propagation delay over  
ECL Pro™  
temperature  
3.3V and 5V power supply options  
DESCRIPTION  
75internal input pulldown resistor  
Wide operating temperature range: –40°c to +85°C  
Available in 8-Pin (3mm) MSOP and SOIC package  
The SY10EP52V is a differential data, differential clock  
D flip-flop. The device is functionally equivalent to the  
EL52 device.  
Data enters the master portion of the flip-flop when  
CLK is LOW and is transferred to the slave, and thus the  
outputs, upon a positive transition of the CLK. The  
differential clock inputs of the EP52V allow the device to  
be used as a negative edge triggered flip-flop  
The EP52V employs input clamping circuitry so that  
under open input condition (pulled down to V ) the  
EE  
outputs of the device will remain stable.  
PIN NAMES  
TRUTH TABLE  
D
CLK  
Z
Q
L
Pin  
CLK, /CLK  
D, /D  
Function  
ECL Clock Inputs  
L
H
Z
H
ECL Data Input  
Q, /Q  
ECL Data Outputs  
Positive Supply  
Z = LOW to HIGH Transition  
VCC  
VEE  
Negative, 0 Supply  
ECL Pro is a trademark of Micrel, Inc.  
Rev.: F  
Amendment: /0  
M9999-092305  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: September 2005  

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