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SY10EP451LTGTR PDF预览

SY10EP451LTGTR

更新时间: 2024-09-28 04:50:11
品牌 Logo 应用领域
麦瑞 - MICREL 触发器逻辑集成电路
页数 文件大小 规格书
10页 399K
描述
3.3V ECL 6-Bit Differential Register with Master Reset

SY10EP451LTGTR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:TQFP,针数:32
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:10E
JESD-30 代码:S-PQFP-G32JESD-609代码:e4
长度:7 mm逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:6
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
传播延迟(tpd):0.69 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:7 mmBase Number Matches:1

SY10EP451LTGTR 数据手册

 浏览型号SY10EP451LTGTR的Datasheet PDF文件第2页浏览型号SY10EP451LTGTR的Datasheet PDF文件第3页浏览型号SY10EP451LTGTR的Datasheet PDF文件第4页浏览型号SY10EP451LTGTR的Datasheet PDF文件第5页浏览型号SY10EP451LTGTR的Datasheet PDF文件第6页浏览型号SY10EP451LTGTR的Datasheet PDF文件第7页 
SY10/100EP451L  
3.3V ECL 6-Bit Differential Register  
with Master Reset  
General Description  
Features  
The SY10/100EP451L is a 6-bit fully differential register  
with common clock and single-ended Master Reset (MR).  
It is ideal for very high frequency applications where a  
registered data path is necessary.  
450ps typical propagation delay  
Maximum frequency > 3.0GHz typical  
Asynchronous Master Reset  
20ps skew within device, 35ps skew device-to-device  
PECL mode operating range:  
– VCC = 3.0V to 3.6V with VEE = 0V  
NECL mode operating range:  
– VCC = 0V with VEE = –3.0V to –3.6V  
Open input default state  
All inputs have an internal 75kpull-down resistor.  
Differential inputs have an override clamp. Unused  
differential register inputs can be left open and will default  
LOW. When the differential inputs are forced to < VEE  
+1.2V, the clamp will override and force the output to a  
default state.  
The positive transition of CLK (pin 4) will latch the  
registers. Master Reset (MR) HIGH will asynchronously  
reset all registers forcing Q outputs to go LOW.  
Safety clamp on inputs  
Available in 32-pin TQFP  
Applications  
High Speed Logic  
Datasheets and support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
Wireless Communication Systems  
Data Communication Systems  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-030507-A  
March 2007  
hbwhelp@micrel.com or (408) 955-1690  

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