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SY10E175JCTR PDF预览

SY10E175JCTR

更新时间: 2024-02-22 02:04:40
品牌 Logo 应用领域
麦瑞 - MICREL 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 63K
描述
9-BIT LATCH WITH PARITY

SY10E175JCTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, LCC-28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.81
Is Samacsys:N其他特性:WITH PARITY GENERATION
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.48 mm
逻辑集成电路类型:D LATCH湿度敏感等级:1
位数:9功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):132 mA
Prop。Delay @ Nom-Sup:0.8 ns传播延迟(tpd):0.9 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:LOW LEVEL
宽度:11.48 mmBase Number Matches:1

SY10E175JCTR 数据手册

 浏览型号SY10E175JCTR的Datasheet PDF文件第2页浏览型号SY10E175JCTR的Datasheet PDF文件第3页浏览型号SY10E175JCTR的Datasheet PDF文件第4页 
9-BIT LATCH  
WITH PARITY  
SY10E175  
SY100E175  
FEATURES  
DESCRIPTION  
9-bit latch  
The SY10/100E175 are 9-bit latches. They also feature  
a tenth latched output (ODDPAR) which is formed as the  
odd parity of the nine data inputs (ODDPAR is HIGH if  
an odd number of the inputs are HIGH).  
The E175 can also be used to generate byte parity by  
using D8 as the parity-type select (L = even parity, H =  
odd parity) and using ODDPAR as the byte parity output.  
The LEN pin latches the data when asserted with a  
logical high and makes the latch transparent when placed  
at a logic low level.  
Extended 100E VEE range of –4.2V to –5.5V  
Parity detection/generation  
800ps max. D to Output  
Reset  
Internal 75Kinput pull-down resistors  
Fully compatible with Motorola MC10E/100E175  
Available in 28-pin PLCC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
D0  
D
Q
Q0  
EN  
R
25  
24 23 22 21 20 19  
D
5
Q
Q
6
5
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
D
D
4
3
bits  
1 7  
V
CC  
TOP VIEW  
PLCC  
V
EE  
Q
Q
4
3
J28-1  
LEN  
MR  
2
D8  
D
Q
Q8  
V
CCO  
3
EN  
D
2
Q2  
4
R
5
6
7
8
9
10 11  
D
Q
ODDPAR  
EN  
R
PIN NAMES  
LEN  
MR  
Pin  
D0 – D8  
LEN  
Function  
Data Inputs  
Latch Enable  
Master Reset  
Data Outputs  
Parity Output  
VCC to Output  
MR  
Q0 – Q8  
ODDPAR  
VCCO  
Rev.: C  
Amendment:/1  
Issue Date: February, 1998  
1

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